Changeset 7ba7c6d in mainline for kernel/arch/sparc64/src
- Timestamp:
- 2006-10-08T20:09:28Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- e4398200
- Parents:
- 64c2ad5
- Location:
- kernel/arch/sparc64/src
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/src/dummy.s
r64c2ad5 r7ba7c6d 34 34 .global dummy 35 35 36 cpu_sleep: 37 sys_tls_set: 36 cpu_sleep: ! not supported by architecture 37 sys_tls_set: ! not needed on architecture 38 38 39 39 dummy: -
kernel/arch/sparc64/src/trap/trap_table.S
r64c2ad5 r7ba7c6d 747 747 stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC] 748 748 stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC] 749 750 /* 751 * Save the Y register. 752 * This register is deprecated according to SPARC V9 specification 753 * and is only present for backward compatibility with previous 754 * versions of the SPARC architecture. 755 * Surprisingly, gcc makes use of this register without a notice. 756 */ 757 rd %y, %g4 758 stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y] 749 759 750 760 wrpr %g0, 0, %tl … … 776 786 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2 777 787 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3 788 789 /* 790 * Restore Y. 791 */ 792 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4 793 wr %g4, %y 778 794 779 795 /*
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