Index: kernel/arch/mips32/include/asm.h
===================================================================
--- kernel/arch/mips32/include/asm.h	(revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190)
+++ kernel/arch/mips32/include/asm.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -38,9 +38,16 @@
 #include <typedefs.h>
 #include <config.h>
+#include <trace.h>
 
-static inline void cpu_sleep(void)
+NO_TRACE static inline void cpu_sleep(void)
 {
-	/* Most of the simulators do not support */
-/*	asm volatile ("wait"); */
+	/*
+	 * Unfortunatelly most of the simulators do not support
+	 *
+	 * asm volatile (
+	 *     "wait"
+	 * );
+	 *
+	 */
 }
 
@@ -52,5 +59,5 @@
  *
  */
-static inline uintptr_t get_stack_base(void)
+NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t base;
@@ -65,44 +72,43 @@
 }
 
-extern void cpu_halt(void) __attribute__((noreturn));
-extern void asm_delay_loop(uint32_t t);
-extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg,
-    uintptr_t entry);
-
-extern ipl_t interrupts_disable(void);
-extern ipl_t interrupts_enable(void);
-extern void interrupts_restore(ipl_t ipl);
-extern ipl_t interrupts_read(void);
-extern bool interrupts_disabled(void);
-
-static inline void pio_write_8(ioport8_t *port, uint8_t v)
+NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
 }
 
-static inline void pio_write_16(ioport16_t *port, uint16_t v)
+NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
 }
 
-static inline void pio_write_32(ioport32_t *port, uint32_t v)
+NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
 }
 
-static inline uint8_t pio_read_8(ioport8_t *port)
+NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	return *port;
 }
 
-static inline uint16_t pio_read_16(ioport16_t *port)
+NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	return *port;
 }
 
-static inline uint32_t pio_read_32(ioport32_t *port)
+NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	return *port;
 }
+
+extern void cpu_halt(void) __attribute__((noreturn));
+extern void asm_delay_loop(uint32_t);
+extern void userspace_asm(uintptr_t, uintptr_t, uintptr_t);
+
+extern ipl_t interrupts_disable(void);
+extern ipl_t interrupts_enable(void);
+extern void interrupts_restore(ipl_t);
+extern ipl_t interrupts_read(void);
+extern bool interrupts_disabled(void);
 
 #endif
Index: kernel/arch/mips32/include/atomic.h
===================================================================
--- kernel/arch/mips32/include/atomic.h	(revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190)
+++ kernel/arch/mips32/include/atomic.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -36,4 +36,6 @@
 #define KERN_mips32_ATOMIC_H_
 
+#include <trace.h>
+
 #define atomic_inc(x)  ((void) atomic_add(x, 1))
 #define atomic_dec(x)  ((void) atomic_add(x, -1))
@@ -53,5 +55,6 @@
  *
  */
-static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
+NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
+    atomic_count_t i)
 {
 	atomic_count_t tmp;
@@ -76,5 +79,5 @@
 }
 
-static inline atomic_count_t test_and_set(atomic_t *val)
+NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
 {
 	atomic_count_t tmp;
@@ -98,5 +101,5 @@
 }
 
-static inline void atomic_lock_arch(atomic_t *val)
+NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
 {
 	do {
Index: kernel/arch/mips32/include/barrier.h
===================================================================
--- kernel/arch/mips32/include/barrier.h	(revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190)
+++ kernel/arch/mips32/include/barrier.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32	
+/** @addtogroup mips32
  * @{
  */
@@ -39,10 +39,10 @@
  * TODO: implement true MIPS memory barriers for macros below.
  */
-#define CS_ENTER_BARRIER()	asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()	asm volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
-#define memory_barrier()        asm volatile ("" ::: "memory")
-#define read_barrier()          asm volatile ("" ::: "memory")
-#define write_barrier()         asm volatile ("" ::: "memory")
+#define memory_barrier() asm volatile ("" ::: "memory")
+#define read_barrier()   asm volatile ("" ::: "memory")
+#define write_barrier()  asm volatile ("" ::: "memory")
 
 #define smc_coherence(a)
Index: kernel/arch/mips32/include/cycle.h
===================================================================
--- kernel/arch/mips32/include/cycle.h	(revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190)
+++ kernel/arch/mips32/include/cycle.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -38,6 +38,7 @@
 #include <arch/cp0.h>
 #include <arch/interrupt.h>
+#include <trace.h>
 
-static inline uint64_t get_cycle(void)
+NO_TRACE static inline uint64_t get_cycle(void)
 {
 	return ((uint64_t) count_hi << 32) + ((uint64_t) cp0_count_read());
Index: kernel/arch/mips32/include/exception.h
===================================================================
--- kernel/arch/mips32/include/exception.h	(revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190)
+++ kernel/arch/mips32/include/exception.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32	
+/** @addtogroup mips32
  * @{
  */
@@ -38,23 +38,24 @@
 #include <typedefs.h>
 #include <arch/cp0.h>
+#include <trace.h>
 
-#define EXC_Int		0
-#define EXC_Mod		1
-#define EXC_TLBL	2
-#define EXC_TLBS	3
-#define EXC_AdEL	4
-#define EXC_AdES	5
-#define EXC_IBE		6
-#define EXC_DBE		7
-#define EXC_Sys		8
-#define EXC_Bp		9
-#define EXC_RI		10
-#define EXC_CpU		11
-#define EXC_Ov		12
-#define EXC_Tr		13
-#define EXC_VCEI	14
-#define EXC_FPE		15
-#define EXC_WATCH	23
-#define EXC_VCED	31
+#define EXC_Int    0
+#define EXC_Mod    1
+#define EXC_TLBL   2
+#define EXC_TLBS   3
+#define EXC_AdEL   4
+#define EXC_AdES   5
+#define EXC_IBE    6
+#define EXC_DBE    7
+#define EXC_Sys    8
+#define EXC_Bp     9
+#define EXC_RI     10
+#define EXC_CpU    11
+#define EXC_Ov     12
+#define EXC_Tr     13
+#define EXC_VCEI   14
+#define EXC_FPE    15
+#define EXC_WATCH  23
+#define EXC_VCED   31
 
 typedef struct istate {
@@ -82,11 +83,12 @@
 	uint32_t lo;
 	uint32_t hi;
-
-	uint32_t status; /* cp0_status */
-	uint32_t epc; /* cp0_epc */
-	uint32_t k1; /* We use it as thread-local pointer */
+	
+	uint32_t status;  /* cp0_status */
+	uint32_t epc;     /* cp0_epc */
+	uint32_t k1;      /* We use it as thread-local pointer */
 } istate_t;
 
-static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
+NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+    uintptr_t retaddr)
 {
 	istate->epc = retaddr;
@@ -94,15 +96,19 @@
 
 /** Return true if exception happened while in userspace */
-static inline int istate_from_uspace(istate_t *istate)
+NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return istate->status & cp0_status_um_bit;
 }
-static inline unative_t istate_get_pc(istate_t *istate)
+
+NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
 {
 	return istate->epc;
 }
-static inline unative_t istate_get_fp(istate_t *istate)
+
+NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
 {
-	return 0;	/* FIXME */
+	/* FIXME */
+	
+	return 0;
 }
 
Index: kernel/arch/mips32/include/faddr.h
===================================================================
--- kernel/arch/mips32/include/faddr.h	(revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190)
+++ kernel/arch/mips32/include/faddr.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32	
+/** @addtogroup mips32
  * @{
  */
@@ -38,5 +38,5 @@
 #include <typedefs.h>
 
-#define FADDR(fptr)		((uintptr_t) (fptr))
+#define FADDR(fptr)  ((uintptr_t) (fptr))
 
 #endif
Index: kernel/arch/mips32/include/mm/page.h
===================================================================
--- kernel/arch/mips32/include/mm/page.h	(revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190)
+++ kernel/arch/mips32/include/mm/page.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -37,4 +37,5 @@
 
 #include <arch/mm/frame.h>
+#include <trace.h>
 
 #define PAGE_WIDTH	FRAME_WIDTH
@@ -155,5 +156,5 @@
 
 
-static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
+NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
 {
 	pte_t *p = &pt[i];
@@ -168,5 +169,5 @@
 }
 
-static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
+NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_t *p = &pt[i];
Index: kernel/arch/mips32/include/mm/tlb.h
===================================================================
--- kernel/arch/mips32/include/mm/tlb.h	(revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190)
+++ kernel/arch/mips32/include/mm/tlb.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -39,4 +39,5 @@
 #include <arch/mm/asid.h>
 #include <arch/exception.h>
+#include <trace.h>
 
 #define TLB_ENTRY_COUNT  48
@@ -126,5 +127,5 @@
  * Probe TLB for Matching Entry.
  */
-static inline void tlbp(void)
+NO_TRACE static inline void tlbp(void)
 {
 	asm volatile ("tlbp\n\t");
@@ -136,5 +137,5 @@
  * Read Indexed TLB Entry.
  */
-static inline void tlbr(void)
+NO_TRACE static inline void tlbr(void)
 {
 	asm volatile ("tlbr\n\t");
@@ -145,5 +146,5 @@
  * Write Indexed TLB Entry.
  */
-static inline void tlbwi(void)
+NO_TRACE static inline void tlbwi(void)
 {
 	asm volatile ("tlbwi\n\t");
@@ -154,5 +155,5 @@
  * Write Random TLB Entry.
  */
-static inline void tlbwr(void)
+NO_TRACE static inline void tlbwr(void)
 {
 	asm volatile ("tlbwr\n\t");
