Changeset 7a0359b in mainline for kernel/arch/mips32


Ignore:
Timestamp:
2010-07-02T15:42:19Z (15 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bbfdf62
Parents:
e3ee9b9
Message:

improve kernel function tracing

  • add support for more generic kernel sources
  • replace attribute((no_instrument_function)) with NO_TRACE macro (shorter and for future compatibility with different compilers)
  • to be on the safe side, do not instrument most of the inline and static functions (plus some specific non-static functions)

collateral code cleanup (no change in functionality)

Location:
kernel/arch/mips32/include
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/mips32/include/asm.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <config.h>
     40#include <trace.h>
    4041
    41 static inline void cpu_sleep(void)
     42NO_TRACE static inline void cpu_sleep(void)
    4243{
    43         /* Most of the simulators do not support */
    44 /*      asm volatile ("wait"); */
     44        /*
     45         * Unfortunatelly most of the simulators do not support
     46         *
     47         * asm volatile (
     48         *     "wait"
     49         * );
     50         *
     51         */
    4552}
    4653
    … …  
    5259 *
    5360 */
    54 static inline uintptr_t get_stack_base(void)
     61NO_TRACE static inline uintptr_t get_stack_base(void)
    5562{
    5663        uintptr_t base;
    … …  
    6572}
    6673
    67 extern void cpu_halt(void) __attribute__((noreturn));
    68 extern void asm_delay_loop(uint32_t t);
    69 extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg,
    70     uintptr_t entry);
    71 
    72 extern ipl_t interrupts_disable(void);
    73 extern ipl_t interrupts_enable(void);
    74 extern void interrupts_restore(ipl_t ipl);
    75 extern ipl_t interrupts_read(void);
    76 extern bool interrupts_disabled(void);
    77 
    78 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     74NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    7975{
    8076        *port = v;
    8177}
    8278
    83 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     79NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    8480{
    8581        *port = v;
    8682}
    8783
    88 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     84NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    8985{
    9086        *port = v;
    9187}
    9288
    93 static inline uint8_t pio_read_8(ioport8_t *port)
     89NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    9490{
    9591        return *port;
    9692}
    9793
    98 static inline uint16_t pio_read_16(ioport16_t *port)
     94NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    9995{
    10096        return *port;
    10197}
    10298
    103 static inline uint32_t pio_read_32(ioport32_t *port)
     99NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    104100{
    105101        return *port;
    106102}
     103
     104extern void cpu_halt(void) __attribute__((noreturn));
     105extern void asm_delay_loop(uint32_t);
     106extern void userspace_asm(uintptr_t, uintptr_t, uintptr_t);
     107
     108extern ipl_t interrupts_disable(void);
     109extern ipl_t interrupts_enable(void);
     110extern void interrupts_restore(ipl_t);
     111extern ipl_t interrupts_read(void);
     112extern bool interrupts_disabled(void);
    107113
    108114#endif

  • kernel/arch/mips32/include/atomic.h

    re3ee9b9 r7a0359b  
    3636#define KERN_mips32_ATOMIC_H_
    3737
     38#include <trace.h>
     39
    3840#define atomic_inc(x)  ((void) atomic_add(x, 1))
    3941#define atomic_dec(x)  ((void) atomic_add(x, -1))
    … …  
    5355 *
    5456 */
    55 static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
     57NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
     58    atomic_count_t i)
    5659{
    5760        atomic_count_t tmp;
    … …  
    7679}
    7780
    78 static inline atomic_count_t test_and_set(atomic_t *val)
     81NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
    7982{
    8083        atomic_count_t tmp;
    … …  
    98101}
    99102
    100 static inline void atomic_lock_arch(atomic_t *val)
     103NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    101104{
    102105        do {

  • kernel/arch/mips32/include/barrier.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3939 * TODO: implement true MIPS memory barriers for macros below.
    4040 */
    41 #define CS_ENTER_BARRIER()      asm volatile ("" ::: "memory")
    42 #define CS_LEAVE_BARRIER()      asm volatile ("" ::: "memory")
     41#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
     42#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
    4343
    44 #define memory_barrier()        asm volatile ("" ::: "memory")
    45 #define read_barrier()          asm volatile ("" ::: "memory")
    46 #define write_barrier()         asm volatile ("" ::: "memory")
     44#define memory_barrier() asm volatile ("" ::: "memory")
     45#define read_barrier()   asm volatile ("" ::: "memory")
     46#define write_barrier()  asm volatile ("" ::: "memory")
    4747
    4848#define smc_coherence(a)

  • kernel/arch/mips32/include/cycle.h

    re3ee9b9 r7a0359b  
    3838#include <arch/cp0.h>
    3939#include <arch/interrupt.h>
     40#include <trace.h>
    4041
    41 static inline uint64_t get_cycle(void)
     42NO_TRACE static inline uint64_t get_cycle(void)
    4243{
    4344        return ((uint64_t) count_hi << 32) + ((uint64_t) cp0_count_read());

  • kernel/arch/mips32/include/exception.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3838#include <typedefs.h>
    3939#include <arch/cp0.h>
     40#include <trace.h>
    4041
    41 #define EXC_Int         0
    42 #define EXC_Mod         1
    43 #define EXC_TLBL        2
    44 #define EXC_TLBS        3
    45 #define EXC_AdEL        4
    46 #define EXC_AdES        5
    47 #define EXC_IBE         6
    48 #define EXC_DBE         7
    49 #define EXC_Sys         8
    50 #define EXC_Bp          9
    51 #define EXC_RI          10
    52 #define EXC_CpU         11
    53 #define EXC_Ov          12
    54 #define EXC_Tr          13
    55 #define EXC_VCEI        14
    56 #define EXC_FPE         15
    57 #define EXC_WATCH       23
    58 #define EXC_VCED        31
     42#define EXC_Int    0
     43#define EXC_Mod    1
     44#define EXC_TLBL   2
     45#define EXC_TLBS   3
     46#define EXC_AdEL   4
     47#define EXC_AdES   5
     48#define EXC_IBE    6
     49#define EXC_DBE    7
     50#define EXC_Sys    8
     51#define EXC_Bp     9
     52#define EXC_RI     10
     53#define EXC_CpU    11
     54#define EXC_Ov     12
     55#define EXC_Tr     13
     56#define EXC_VCEI   14
     57#define EXC_FPE    15
     58#define EXC_WATCH  23
     59#define EXC_VCED   31
    5960
    6061typedef struct istate {
    … …  
    8283        uint32_t lo;
    8384        uint32_t hi;
    84 
    85         uint32_t status; /* cp0_status */
    86         uint32_t epc; /* cp0_epc */
    87         uint32_t k1; /* We use it as thread-local pointer */
     85       
     86        uint32_t status;  /* cp0_status */
     87        uint32_t epc;     /* cp0_epc */
     88        uint32_t k1;      /* We use it as thread-local pointer */
    8889} istate_t;
    8990
    90 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     91NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     92    uintptr_t retaddr)
    9193{
    9294        istate->epc = retaddr;
    … …  
    9496
    9597/** Return true if exception happened while in userspace */
    96 static inline int istate_from_uspace(istate_t *istate)
     98NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    9799{
    98100        return istate->status & cp0_status_um_bit;
    99101}
    100 static inline unative_t istate_get_pc(istate_t *istate)
     102
     103NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    101104{
    102105        return istate->epc;
    103106}
    104 static inline unative_t istate_get_fp(istate_t *istate)
     107
     108NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    105109{
    106         return 0;       /* FIXME */
     110        /* FIXME */
     111       
     112        return 0;
    107113}
    108114

  • kernel/arch/mips32/include/faddr.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3838#include <typedefs.h>
    3939
    40 #define FADDR(fptr)             ((uintptr_t) (fptr))
     40#define FADDR(fptr)  ((uintptr_t) (fptr))
    4141
    4242#endif

  • kernel/arch/mips32/include/mm/page.h

    re3ee9b9 r7a0359b  
    3737
    3838#include <arch/mm/frame.h>
     39#include <trace.h>
    3940
    4041#define PAGE_WIDTH      FRAME_WIDTH
    … …  
    155156
    156157
    157 static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     158NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    158159{
    159160        pte_t *p = &pt[i];
    … …  
    168169}
    169170
    170 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     171NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    171172{
    172173        pte_t *p = &pt[i];

  • kernel/arch/mips32/include/mm/tlb.h

    re3ee9b9 r7a0359b  
    3939#include <arch/mm/asid.h>
    4040#include <arch/exception.h>
     41#include <trace.h>
    4142
    4243#define TLB_ENTRY_COUNT  48
    … …  
    126127 * Probe TLB for Matching Entry.
    127128 */
    128 static inline void tlbp(void)
     129NO_TRACE static inline void tlbp(void)
    129130{
    130131        asm volatile ("tlbp\n\t");
    … …  
    136137 * Read Indexed TLB Entry.
    137138 */
    138 static inline void tlbr(void)
     139NO_TRACE static inline void tlbr(void)
    139140{
    140141        asm volatile ("tlbr\n\t");
    … …  
    145146 * Write Indexed TLB Entry.
    146147 */
    147 static inline void tlbwi(void)
     148NO_TRACE static inline void tlbwi(void)
    148149{
    149150        asm volatile ("tlbwi\n\t");
    … …  
    154155 * Write Random TLB Entry.
    155156 */
    156 static inline void tlbwr(void)
     157NO_TRACE static inline void tlbwr(void)
    157158{
    158159        asm volatile ("tlbwr\n\t");
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