Changeset 7a0359b in mainline for kernel/arch/ia64/include


Ignore:
Timestamp:
2010-07-02T15:42:19Z (15 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bbfdf62
Parents:
e3ee9b9
Message:

improve kernel function tracing

  • add support for more generic kernel sources
  • replace attribute((no_instrument_function)) with NO_TRACE macro (shorter and for future compatibility with different compilers)
  • to be on the safe side, do not instrument most of the inline and static functions (plus some specific non-static functions)

collateral code cleanup (no change in functionality)

Location:
kernel/arch/ia64/include
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/ia64/include/asm.h

    re3ee9b9 r7a0359b  
    4040#include <typedefs.h>
    4141#include <arch/register.h>
     42#include <trace.h>
    4243
    4344#define IA64_IOSPACE_ADDRESS  0xE001000000000000ULL
    4445
    45 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     46NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    4647{
    4748        uintptr_t prt = (uintptr_t) port;
    … …  
    5657}
    5758
    58 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     59NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    5960{
    6061        uintptr_t prt = (uintptr_t) port;
    … …  
    6970}
    7071
    71 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     72NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    7273{
    7374        uintptr_t prt = (uintptr_t) port;
    … …  
    8283}
    8384
    84 static inline uint8_t pio_read_8(ioport8_t *port)
     85NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    8586{
    8687        uintptr_t prt = (uintptr_t) port;
    … …  
    9596}
    9697
    97 static inline uint16_t pio_read_16(ioport16_t *port)
     98NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    9899{
    99100        uintptr_t prt = (uintptr_t) port;
    … …  
    108109}
    109110
    110 static inline uint32_t pio_read_32(ioport32_t *port)
     111NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    111112{
    112113        uintptr_t prt = (uintptr_t) port;
    … …  
    126127 * The stack is assumed to be STACK_SIZE long.
    127128 * The stack must start on page boundary.
    128  */
    129 static inline uintptr_t get_stack_base(void)
    130 {
    131         uint64_t v;
    132        
    133         /* I'm not sure why but this code bad inlines in scheduler,
    134            so THE shifts about 16B and causes kernel panic
    135            
    136            asm volatile (
    137                "and %[value] = %[mask], r12"
    138                : [value] "=r" (v)
    139                : [mask] "r" (~(STACK_SIZE - 1))
    140            );
    141            return v;
    142            
    143            This code have the same meaning but inlines well.
    144         */
     129 *
     130 */
     131NO_TRACE static inline uintptr_t get_stack_base(void)
     132{
     133        uint64_t v;
     134       
     135        /*
     136         * I'm not sure why but this code inlines badly
     137         * in scheduler, resulting in THE shifting about
     138         * 16B and causing kernel panic.
     139         *
     140         * asm volatile (
     141         *     "and %[value] = %[mask], r12"
     142         *     : [value] "=r" (v)
     143         *     : [mask] "r" (~(STACK_SIZE - 1))
     144         * );
     145         * return v;
     146         *
     147         * The following code has the same semantics but
     148         * inlines correctly.
     149         *
     150         */
    145151       
    146152        asm volatile (
    … …  
    155161 *
    156162 * @return PSR.
    157  */
    158 static inline uint64_t psr_read(void)
     163 *
     164 */
     165NO_TRACE static inline uint64_t psr_read(void)
    159166{
    160167        uint64_t v;
    … …  
    171178 *
    172179 * @return Return location of interruption vector table.
    173  */
    174 static inline uint64_t iva_read(void)
     180 *
     181 */
     182NO_TRACE static inline uint64_t iva_read(void)
    175183{
    176184        uint64_t v;
    … …  
    187195 *
    188196 * @param v New location of interruption vector table.
    189  */
    190 static inline void iva_write(uint64_t v)
     197 *
     198 */
     199NO_TRACE static inline void iva_write(uint64_t v)
    191200{
    192201        asm volatile (
    … …  
    196205}
    197206
    198 
    199207/** Read IVR (External Interrupt Vector Register).
    200208 *
    201  * @return Highest priority, pending, unmasked external interrupt vector.
    202  */
    203 static inline uint64_t ivr_read(void)
     209 * @return Highest priority, pending, unmasked external
     210 *         interrupt vector.
     211 *
     212 */
     213NO_TRACE static inline uint64_t ivr_read(void)
    204214{
    205215        uint64_t v;
    … …  
    213223}
    214224
    215 static inline uint64_t cr64_read(void)
     225NO_TRACE static inline uint64_t cr64_read(void)
    216226{
    217227        uint64_t v;
    … …  
    225235}
    226236
    227 
    228237/** Write ITC (Interval Timer Counter) register.
    229238 *
    230239 * @param v New counter value.
    231  */
    232 static inline void itc_write(uint64_t v)
     240 *
     241 */
     242NO_TRACE static inline void itc_write(uint64_t v)
    233243{
    234244        asm volatile (
    … …  
    241251 *
    242252 * @return Current counter value.
    243  */
    244 static inline uint64_t itc_read(void)
     253 *
     254 */
     255NO_TRACE static inline uint64_t itc_read(void)
    245256{
    246257        uint64_t v;
    … …  
    257268 *
    258269 * @param v New match value.
    259  */
    260 static inline void itm_write(uint64_t v)
     270 *
     271 */
     272NO_TRACE static inline void itm_write(uint64_t v)
    261273{
    262274        asm volatile (
    … …  
    269281 *
    270282 * @return Match value.
    271  */
    272 static inline uint64_t itm_read(void)
     283 *
     284 */
     285NO_TRACE static inline uint64_t itm_read(void)
    273286{
    274287        uint64_t v;
    … …  
    285298 *
    286299 * @return Current vector and mask bit.
    287  */
    288 static inline uint64_t itv_read(void)
     300 *
     301 */
     302NO_TRACE static inline uint64_t itv_read(void)
    289303{
    290304        uint64_t v;
    … …  
    301315 *
    302316 * @param v New vector and mask bit.
    303  */
    304 static inline void itv_write(uint64_t v)
     317 *
     318 */
     319NO_TRACE static inline void itv_write(uint64_t v)
    305320{
    306321        asm volatile (
    … …  
    313328 *
    314329 * @param v This value is ignored.
    315  */
    316 static inline void eoi_write(uint64_t v)
     330 *
     331 */
     332NO_TRACE static inline void eoi_write(uint64_t v)
    317333{
    318334        asm volatile (
    … …  
    325341 *
    326342 * @return Current value of TPR.
    327  */
    328 static inline uint64_t tpr_read(void)
     343 *
     344 */
     345NO_TRACE static inline uint64_t tpr_read(void)
    329346{
    330347        uint64_t v;
    … …  
    341358 *
    342359 * @param v New value of TPR.
    343  */
    344 static inline void tpr_write(uint64_t v)
     360 *
     361 */
     362NO_TRACE static inline void tpr_write(uint64_t v)
    345363{
    346364        asm volatile (
    … …  
    356374 *
    357375 * @return Old interrupt priority level.
    358  */
    359 static ipl_t interrupts_disable(void)
     376 *
     377 */
     378NO_TRACE static ipl_t interrupts_disable(void)
    360379{
    361380        uint64_t v;
    … …  
    377396 *
    378397 * @return Old interrupt priority level.
    379  */
    380 static ipl_t interrupts_enable(void)
     398 *
     399 */
     400NO_TRACE static ipl_t interrupts_enable(void)
    381401{
    382402        uint64_t v;
    … …  
    399419 *
    400420 * @param ipl Saved interrupt priority level.
    401  */
    402 static inline void interrupts_restore(ipl_t ipl)
     421 *
     422 */
     423NO_TRACE static inline void interrupts_restore(ipl_t ipl)
    403424{
    404425        if (ipl & PSR_I_MASK)
    … …  
    411432 *
    412433 * @return PSR.
    413  */
    414 static inline ipl_t interrupts_read(void)
     434 *
     435 */
     436NO_TRACE static inline ipl_t interrupts_read(void)
    415437{
    416438        return (ipl_t) psr_read();
    … …  
    422444 *
    423445 */
    424 static inline bool interrupts_disabled(void)
     446NO_TRACE static inline bool interrupts_disabled(void)
    425447{
    426448        return !(psr_read() & PSR_I_MASK);
    … …  
    428450
    429451/** Disable protection key checking. */
    430 static inline void pk_disable(void)
     452NO_TRACE static inline void pk_disable(void)
    431453{
    432454        asm volatile (

  • kernel/arch/ia64/include/atomic.h

    re3ee9b9 r7a0359b  
    3636#define KERN_ia64_ATOMIC_H_
    3737
    38 static inline atomic_count_t test_and_set(atomic_t *val)
     38#include <trace.h>
     39
     40NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
    3941{
    4042        atomic_count_t v;
    … …  
    5052}
    5153
    52 static inline void atomic_lock_arch(atomic_t *val)
     54NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    5355{
    5456        do {
    … …  
    5759}
    5860
    59 static inline void atomic_inc(atomic_t *val)
     61NO_TRACE static inline void atomic_inc(atomic_t *val)
    6062{
    6163        atomic_count_t v;
    … …  
    6870}
    6971
    70 static inline void atomic_dec(atomic_t *val)
     72NO_TRACE static inline void atomic_dec(atomic_t *val)
    7173{
    7274        atomic_count_t v;
    … …  
    7981}
    8082
    81 static inline atomic_count_t atomic_preinc(atomic_t *val)
     83NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
    8284{
    8385        atomic_count_t v;
    … …  
    9294}
    9395
    94 static inline atomic_count_t atomic_predec(atomic_t *val)
     96NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
    9597{
    9698        atomic_count_t v;
    … …  
    105107}
    106108
    107 static inline atomic_count_t atomic_postinc(atomic_t *val)
     109NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    108110{
    109111        atomic_count_t v;
    … …  
    118120}
    119121
    120 static inline atomic_count_t atomic_postdec(atomic_t *val)
     122NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    121123{
    122124        atomic_count_t v;

  • kernel/arch/ia64/include/cpu.h

    re3ee9b9 r7a0359b  
    4040#include <arch/asm.h>
    4141#include <arch/bootinfo.h>
     42#include <trace.h>
    4243
    43 #define FAMILY_ITANIUM  0x7
    44 #define FAMILY_ITANIUM2 0x1f
     44#define FAMILY_ITANIUM   0x7
     45#define FAMILY_ITANIUM2  0x1f
     46
     47#define CR64_ID_SHIFT   24
     48#define CR64_ID_MASK    0xff000000
     49#define CR64_EID_SHIFT  16
     50#define CR64_EID_MASK   0xff0000
    4551
    4652typedef struct {
    … …  
    5561 *
    5662 * @return Value of CPUID[n] register.
     63 *
    5764 */
    58 static inline uint64_t cpuid_read(int n)
     65NO_TRACE static inline uint64_t cpuid_read(int n)
    5966{
    6067        uint64_t v;
    6168       
    62         asm volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n));
     69        asm volatile (
     70                "mov %[v] = cpuid[%[r]]\n"
     71                : [v] "=r" (v)
     72                : [r] "r" (n)
     73        );
    6374       
    6475        return v;
    6576}
    6677
    67 
    68 #define CR64_ID_SHIFT 24
    69 #define CR64_ID_MASK 0xff000000
    70 #define CR64_EID_SHIFT 16
    71 #define CR64_EID_MASK 0xff0000
    72 
    73 static inline int ia64_get_cpu_id(void)
     78NO_TRACE static inline int ia64_get_cpu_id(void)
    7479{
    75         uint64_t cr64=cr64_read();
    76         return ((CR64_ID_MASK)&cr64)>>CR64_ID_SHIFT;
     80        uint64_t cr64 = cr64_read();
     81        return ((CR64_ID_MASK) &cr64) >> CR64_ID_SHIFT;
    7782}
    7883
    79 static inline int ia64_get_cpu_eid(void)
     84NO_TRACE static inline int ia64_get_cpu_eid(void)
    8085{
    81         uint64_t cr64=cr64_read();
    82         return ((CR64_EID_MASK)&cr64)>>CR64_EID_SHIFT;
     86        uint64_t cr64 = cr64_read();
     87        return ((CR64_EID_MASK) &cr64) >> CR64_EID_SHIFT;
    8388}
    8489
    85 
    86 static inline void ipi_send_ipi(int id, int eid, int intno)
     90NO_TRACE static inline void ipi_send_ipi(int id, int eid, int intno)
    8791{
    8892        (bootinfo->sapic)[2 * (id * 256 + eid)] = intno;
    8993        srlz_d();
    90 
    9194}
    9295

  • kernel/arch/ia64/include/cycle.h

    re3ee9b9 r7a0359b  
    3636#define KERN_ia64_CYCLE_H_
    3737
    38 static inline uint64_t get_cycle(void)
     38#include <trace.h>
     39
     40NO_TRACE static inline uint64_t get_cycle(void)
    3941{
    4042        return 0;

  • kernel/arch/ia64/include/interrupt.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <arch/register.h>
     40#include <trace.h>
    4041
    4142/** ia64 has 256 INRs. */
    … …  
    133134} istate_t;
    134135
    135 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     136extern void *ivt;
     137
     138NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     139    uintptr_t retaddr)
    136140{
    137141        istate->cr_iip = retaddr;
    … …  
    139143}
    140144
    141 static inline unative_t istate_get_pc(istate_t *istate)
     145NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    142146{
    143147        return istate->cr_iip;
    144148}
    145149
    146 static inline unative_t istate_get_fp(istate_t *istate)
     150NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    147151{
    148         return 0;       /* FIXME */
     152        /* FIXME */
     153       
     154        return 0;
    149155}
    150156
    151 static inline int istate_from_uspace(istate_t *istate)
     157NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    152158{
    153159        return (istate->cr_iip) < 0xe000000000000000ULL;
    154160}
    155161
    156 extern void *ivt;
     162extern void general_exception(uint64_t, istate_t *);
     163extern int break_instruction(uint64_t, istate_t *);
     164extern void universal_handler(uint64_t, istate_t *);
     165extern void nop_handler(uint64_t, istate_t *);
     166extern void external_interrupt(uint64_t, istate_t *);
     167extern void disabled_fp_register(uint64_t, istate_t *);
    157168
    158 extern void general_exception(uint64_t vector, istate_t *istate);
    159 extern int break_instruction(uint64_t vector, istate_t *istate);
    160 extern void universal_handler(uint64_t vector, istate_t *istate);
    161 extern void nop_handler(uint64_t vector, istate_t *istate);
    162 extern void external_interrupt(uint64_t vector, istate_t *istate);
    163 extern void disabled_fp_register(uint64_t vector, istate_t *istate);
    164 
    165 extern void trap_virtual_enable_irqs(uint16_t irqmask);
     169extern void trap_virtual_enable_irqs(uint16_t);
    166170
    167171#endif

  • kernel/arch/ia64/include/mm/page.h

    re3ee9b9 r7a0359b  
    208208 * @return Address of the head of VHPT collision chain.
    209209 */
    210 static inline uint64_t thash(uint64_t va)
     210NO_TRACE static inline uint64_t thash(uint64_t va)
    211211{
    212212        uint64_t ret;
    … …  
    230230 * @return The unique tag for VPN and RID in the collision chain returned by thash().
    231231 */
    232 static inline uint64_t ttag(uint64_t va)
     232NO_TRACE static inline uint64_t ttag(uint64_t va)
    233233{
    234234        uint64_t ret;
    … …  
    249249 * @return Current contents of rr[i].
    250250 */
    251 static inline uint64_t rr_read(size_t i)
     251NO_TRACE static inline uint64_t rr_read(size_t i)
    252252{
    253253        uint64_t ret;
    … …  
    269269 * @param v Value to be written to rr[i].
    270270 */
    271 static inline void rr_write(size_t i, uint64_t v)
     271NO_TRACE static inline void rr_write(size_t i, uint64_t v)
    272272{
    273273        ASSERT(i < REGION_REGISTERS);
    … …  
    284284 * @return Current value stored in PTA.
    285285 */
    286 static inline uint64_t pta_read(void)
     286NO_TRACE static inline uint64_t pta_read(void)
    287287{
    288288        uint64_t ret;
    … …  
    300300 * @param v New value to be stored in PTA.
    301301 */
    302 static inline void pta_write(uint64_t v)
     302NO_TRACE static inline void pta_write(uint64_t v)
    303303{
    304304        asm volatile (
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