Index: kernel/arch/ia32/include/asm.h
===================================================================
--- kernel/arch/ia32/include/asm.h	(revision b5382d4f551b38012fe4db27dd79c095f5e09706)
+++ kernel/arch/ia32/include/asm.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -41,18 +41,8 @@
 #include <typedefs.h>
 #include <config.h>
+#include <trace.h>
 
 extern uint32_t interrupt_handler_size;
 
-extern void paging_on(void);
-
-extern void interrupt_handlers(void);
-
-extern void enable_l_apic_in_msr(void);
-
-
-extern void asm_delay_loop(uint32_t t);
-extern void asm_fake_loop(uint32_t t);
-
-
 /** Halt CPU
  *
@@ -60,5 +50,5 @@
  *
  */
-static inline __attribute__((noreturn)) void cpu_halt(void)
+NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
 {
 	while (true) {
@@ -69,10 +59,12 @@
 }
 
-static inline void cpu_sleep(void)
-{
-	asm volatile ("hlt\n");
-}
-
-#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
+NO_TRACE static inline void cpu_sleep(void)
+{
+	asm volatile (
+		"hlt\n"
+	);
+}
+
+#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
 	{ \
 		unative_t res; \
@@ -84,5 +76,5 @@
 	}
 
-#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
+#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
 	{ \
 		asm volatile ( \
@@ -119,9 +111,10 @@
  *
  */
-static inline void pio_write_8(ioport8_t *port, uint8_t val)
+NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
 	asm volatile (
 		"outb %b[val], %w[port]\n"
-		:: [val] "a" (val), [port] "d" (port)
+		:: [val] "a" (val),
+		   [port] "d" (port)
 	);
 }
@@ -135,9 +128,10 @@
  *
  */
-static inline void pio_write_16(ioport16_t *port, uint16_t val)
+NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
 	asm volatile (
 		"outw %w[val], %w[port]\n"
-		:: [val] "a" (val), [port] "d" (port)
+		:: [val] "a" (val),
+		   [port] "d" (port)
 	);
 }
@@ -151,9 +145,10 @@
  *
  */
-static inline void pio_write_32(ioport32_t *port, uint32_t val)
+NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
 	asm volatile (
 		"outl %[val], %w[port]\n"
-		:: [val] "a" (val), [port] "d" (port)
+		:: [val] "a" (val),
+		   [port] "d" (port)
 	);
 }
@@ -167,5 +162,5 @@
  *
  */
-static inline uint8_t pio_read_8(ioport8_t *port)
+NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	uint8_t val;
@@ -188,5 +183,5 @@
  *
  */
-static inline uint16_t pio_read_16(ioport16_t *port)
+NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	uint16_t val;
@@ -209,5 +204,5 @@
  *
  */
-static inline uint32_t pio_read_32(ioport32_t *port)
+NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	uint32_t val;
@@ -230,5 +225,5 @@
  *
  */
-static inline ipl_t interrupts_enable(void)
+NO_TRACE static inline ipl_t interrupts_enable(void)
 {
 	ipl_t v;
@@ -252,5 +247,5 @@
  *
  */
-static inline ipl_t interrupts_disable(void)
+NO_TRACE static inline ipl_t interrupts_disable(void)
 {
 	ipl_t v;
@@ -273,5 +268,5 @@
  *
  */
-static inline void interrupts_restore(ipl_t ipl)
+NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	asm volatile (
@@ -287,5 +282,5 @@
  *
  */
-static inline ipl_t interrupts_read(void)
+NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	ipl_t v;
@@ -305,5 +300,5 @@
  *
  */
-static inline bool interrupts_disabled(void)
+NO_TRACE static inline bool interrupts_disabled(void)
 {
 	ipl_t v;
@@ -319,14 +314,15 @@
 
 /** Write to MSR */
-static inline void write_msr(uint32_t msr, uint64_t value)
+NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
 {
 	asm volatile (
 		"wrmsr"
-		:: "c" (msr), "a" ((uint32_t) (value)),
+		:: "c" (msr),
+		   "a" ((uint32_t) (value)),
 		   "d" ((uint32_t) (value >> 32))
 	);
 }
 
-static inline uint64_t read_msr(uint32_t msr)
+NO_TRACE static inline uint64_t read_msr(uint32_t msr)
 {
 	uint32_t ax, dx;
@@ -334,5 +330,6 @@
 	asm volatile (
 		"rdmsr"
-		: "=a" (ax), "=d" (dx)
+		: "=a" (ax),
+		  "=d" (dx)
 		: "c" (msr)
 	);
@@ -349,5 +346,5 @@
  *
  */
-static inline uintptr_t get_stack_base(void)
+NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t v;
@@ -367,5 +364,5 @@
  *
  */
-static inline void invlpg(uintptr_t addr)
+NO_TRACE static inline void invlpg(uintptr_t addr)
 {
 	asm volatile (
@@ -380,5 +377,5 @@
  *
  */
-static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
+NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
 {
 	asm volatile (
@@ -393,5 +390,5 @@
  *
  */
-static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
+NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
 {
 	asm volatile (
@@ -406,5 +403,5 @@
  *
  */
-static inline void idtr_load(ptr_16_32_t *idtr_reg)
+NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
 {
 	asm volatile (
@@ -419,5 +416,5 @@
  *
  */
-static inline void tr_load(uint16_t sel)
+NO_TRACE static inline void tr_load(uint16_t sel)
 {
 	asm volatile (
@@ -427,4 +424,11 @@
 }
 
+extern void paging_on(void);
+extern void interrupt_handlers(void);
+extern void enable_l_apic_in_msr(void);
+
+extern void asm_delay_loop(uint32_t);
+extern void asm_fake_loop(uint32_t);
+
 #endif
 
Index: kernel/arch/ia32/include/atomic.h
===================================================================
--- kernel/arch/ia32/include/atomic.h	(revision b5382d4f551b38012fe4db27dd79c095f5e09706)
+++ kernel/arch/ia32/include/atomic.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -39,6 +39,7 @@
 #include <arch/barrier.h>
 #include <preemption.h>
+#include <trace.h>
 
-static inline void atomic_inc(atomic_t *val)
+NO_TRACE static inline void atomic_inc(atomic_t *val)
 {
 #ifdef CONFIG_SMP
@@ -55,5 +56,5 @@
 }
 
-static inline void atomic_dec(atomic_t *val)
+NO_TRACE static inline void atomic_dec(atomic_t *val)
 {
 #ifdef CONFIG_SMP
@@ -70,5 +71,5 @@
 }
 
-static inline atomic_count_t atomic_postinc(atomic_t *val)
+NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
 {
 	atomic_count_t r = 1;
@@ -83,5 +84,5 @@
 }
 
-static inline atomic_count_t atomic_postdec(atomic_t *val)
+NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
 {
 	atomic_count_t r = -1;
@@ -99,5 +100,5 @@
 #define atomic_predec(val)  (atomic_postdec(val) - 1)
 
-static inline atomic_count_t test_and_set(atomic_t *val)
+NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
 {
 	atomic_count_t v = 1;
@@ -113,5 +114,5 @@
 
 /** ia32 specific fast spinlock */
-static inline void atomic_lock_arch(atomic_t *val)
+NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
 {
 	atomic_count_t tmp;
Index: kernel/arch/ia32/include/barrier.h
===================================================================
--- kernel/arch/ia32/include/barrier.h	(revision b5382d4f551b38012fe4db27dd79c095f5e09706)
+++ kernel/arch/ia32/include/barrier.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -36,4 +36,6 @@
 #define KERN_ia32_BARRIER_H_
 
+#include <trace.h>
+
 /*
  * NOTE:
@@ -50,5 +52,5 @@
 #define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
-static inline void cpuid_serialization(void)
+NO_TRACE static inline void cpuid_serialization(void)
 {
 	asm volatile (
Index: kernel/arch/ia32/include/cycle.h
===================================================================
--- kernel/arch/ia32/include/cycle.h	(revision b5382d4f551b38012fe4db27dd79c095f5e09706)
+++ kernel/arch/ia32/include/cycle.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia32	
+/** @addtogroup ia32
  * @{
  */
@@ -36,5 +36,7 @@
 #define KERN_ia32_CYCLE_H_
 
-static inline uint64_t get_cycle(void)
+#include <trace.h>
+
+NO_TRACE static inline uint64_t get_cycle(void)
 {
 	uint64_t v;
Index: kernel/arch/ia32/include/interrupt.h
===================================================================
--- kernel/arch/ia32/include/interrupt.h	(revision b5382d4f551b38012fe4db27dd79c095f5e09706)
+++ kernel/arch/ia32/include/interrupt.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -38,24 +38,25 @@
 #include <typedefs.h>
 #include <arch/pm.h>
+#include <trace.h>
 
-#define IVT_ITEMS	IDT_ITEMS
-#define IVT_FIRST	0
+#define IVT_ITEMS  IDT_ITEMS
+#define IVT_FIRST  0
 
-#define EXC_COUNT	32
-#define IRQ_COUNT	16
+#define EXC_COUNT  32
+#define IRQ_COUNT  16
 
-#define IVT_EXCBASE	0
-#define IVT_IRQBASE	(IVT_EXCBASE + EXC_COUNT)
-#define IVT_FREEBASE	(IVT_IRQBASE + IRQ_COUNT)
+#define IVT_EXCBASE   0
+#define IVT_IRQBASE   (IVT_EXCBASE + EXC_COUNT)
+#define IVT_FREEBASE  (IVT_IRQBASE + IRQ_COUNT)
 
-#define IRQ_CLK		0
-#define IRQ_KBD		1
-#define IRQ_PIC1	2
-#define IRQ_PIC_SPUR	7
-#define IRQ_MOUSE	12
-#define IRQ_DP8390	9
+#define IRQ_CLK       0
+#define IRQ_KBD       1
+#define IRQ_PIC1      2
+#define IRQ_PIC_SPUR  7
+#define IRQ_MOUSE     12
+#define IRQ_DP8390    9
 
-/* this one must have four least significant bits set to ones */
-#define VECTOR_APIC_SPUR	(IVT_ITEMS - 1)
+/* This one must have four least significant bits set to ones */
+#define VECTOR_APIC_SPUR  (IVT_ITEMS - 1)
 
 #if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
@@ -63,10 +64,10 @@
 #endif
 
-#define VECTOR_DEBUG			1
-#define VECTOR_CLK			(IVT_IRQBASE + IRQ_CLK)
-#define VECTOR_PIC_SPUR			(IVT_IRQBASE + IRQ_PIC_SPUR)
-#define VECTOR_SYSCALL			IVT_FREEBASE
-#define VECTOR_TLB_SHOOTDOWN_IPI	(IVT_FREEBASE + 1)
-#define VECTOR_DEBUG_IPI		(IVT_FREEBASE + 2)
+#define VECTOR_DEBUG              1
+#define VECTOR_CLK                (IVT_IRQBASE + IRQ_CLK)
+#define VECTOR_PIC_SPUR           (IVT_IRQBASE + IRQ_PIC_SPUR)
+#define VECTOR_SYSCALL            IVT_FREEBASE
+#define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
+#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
 
 typedef struct istate {
@@ -79,48 +80,49 @@
 	uint32_t ebp;
 	
-	uint32_t ebp_frame;	/* imitation of frame pointer linkage */
-	uint32_t eip_frame;	/* imitation of return address linkage */
-
+	uint32_t ebp_frame;  /* imitation of frame pointer linkage */
+	uint32_t eip_frame;  /* imitation of return address linkage */
+	
 	uint32_t gs;
 	uint32_t fs;
 	uint32_t es;
 	uint32_t ds;
-
-	uint32_t error_word;	/* real or fake error word */
+	
+	uint32_t error_word;  /* real or fake error word */
 	uint32_t eip;
 	uint32_t cs;
 	uint32_t eflags;
-	uint32_t esp;		/* only if istate_t is from uspace */
-	uint32_t ss;		/* only if istate_t is from uspace */
+	uint32_t esp;         /* only if istate_t is from uspace */
+	uint32_t ss;          /* only if istate_t is from uspace */
 } istate_t;
 
 /** Return true if exception happened while in userspace */
-static inline int istate_from_uspace(istate_t *istate)
+NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return !(istate->eip & 0x80000000);
 }
 
-static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
+NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+    uintptr_t retaddr)
 {
 	istate->eip = retaddr;
 }
 
-static inline unative_t istate_get_pc(istate_t *istate)
+NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
 {
 	return istate->eip;
 }
 
-static inline unative_t istate_get_fp(istate_t *istate)
+NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
 {
 	return istate->ebp;
 }
 
-extern void (* disable_irqs_function)(uint16_t irqmask);
-extern void (* enable_irqs_function)(uint16_t irqmask);
+extern void (* disable_irqs_function)(uint16_t);
+extern void (* enable_irqs_function)(uint16_t);
 extern void (* eoi_function)(void);
 
 extern void interrupt_init(void);
-extern void trap_virtual_enable_irqs(uint16_t irqmask);
-extern void trap_virtual_disable_irqs(uint16_t irqmask);
+extern void trap_virtual_enable_irqs(uint16_t);
+extern void trap_virtual_disable_irqs(uint16_t);
 
 #endif
Index: kernel/arch/ia32/include/mm/page.h
===================================================================
--- kernel/arch/ia32/include/mm/page.h	(revision b5382d4f551b38012fe4db27dd79c095f5e09706)
+++ kernel/arch/ia32/include/mm/page.h	(revision 7a0359b903311f67678b4a0a3ebbcf0daf6eab38)
@@ -37,4 +37,5 @@
 
 #include <arch/mm/frame.h>
+#include <trace.h>
 
 #define PAGE_WIDTH	FRAME_WIDTH
@@ -161,5 +162,5 @@
 } __attribute__ ((packed)) pte_t;
 
-static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
+NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
 {
 	pte_t *p = &pt[i];
@@ -174,5 +175,5 @@
 }
 
-static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
+NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_t *p = &pt[i];
