Changeset 7a0359b in mainline for kernel/arch/arm32


Ignore:
Timestamp:
2010-07-02T15:42:19Z (15 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bbfdf62
Parents:
e3ee9b9
Message:

improve kernel function tracing

  • add support for more generic kernel sources
  • replace attribute((no_instrument_function)) with NO_TRACE macro (shorter and for future compatibility with different compilers)
  • to be on the safe side, do not instrument most of the inline and static functions (plus some specific non-static functions)

collateral code cleanup (no change in functionality)

Location:
kernel/arch/arm32/include
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/include/asm.h

    re3ee9b9 r7a0359b  
    4141#include <config.h>
    4242#include <arch/interrupt.h>
     43#include <trace.h>
    4344
    4445/** No such instruction on ARM to sleep CPU. */
    45 static inline void cpu_sleep(void)
     46NO_TRACE static inline void cpu_sleep(void)
    4647{
    4748}
    4849
    49 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     50NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    5051{
    5152        *port = v;
    5253}
    5354
    54 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     55NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    5556{
    5657        *port = v;
    5758}
    5859
    59 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     60NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    6061{
    6162        *port = v;
    6263}
    6364
    64 static inline uint8_t pio_read_8(ioport8_t *port)
     65NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    6566{
    6667        return *port;
    6768}
    6869
    69 static inline uint16_t pio_read_16(ioport16_t *port)
     70NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    7071{
    7172        return *port;
    7273}
    7374
    74 static inline uint32_t pio_read_32(ioport32_t *port)
     75NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    7576{
    7677        return *port;
    … …  
    8485 *
    8586 */
    86 static inline uintptr_t get_stack_base(void)
     87NO_TRACE static inline uintptr_t get_stack_base(void)
    8788{
    8889        uintptr_t v;
     90       
    8991        asm volatile (
    9092                "and %[v], sp, %[size]\n"
    … …  
    9294                : [size] "r" (~(STACK_SIZE - 1))
    9395        );
     96       
    9497        return v;
    9598}

  • kernel/arch/arm32/include/atomic.h

    re3ee9b9 r7a0359b  
    3838
    3939#include <arch/asm.h>
     40#include <trace.h>
    4041
    4142/** Atomic addition.
    … …  
    4748 *
    4849 */
    49 static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
     50NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
     51    atomic_count_t i)
    5052{
    5153        /*
    … …  
    6668 *
    6769 */
    68 static inline void atomic_inc(atomic_t *val)
     70NO_TRACE static inline void atomic_inc(atomic_t *val)
    6971{
    7072        atomic_add(val, 1);
    … …  
    7678 *
    7779 */
    78 static inline void atomic_dec(atomic_t *val) {
     80NO_TRACE static inline void atomic_dec(atomic_t *val) {
    7981        atomic_add(val, -1);
    8082}
    … …  
    8688 *
    8789 */
    88 static inline atomic_count_t atomic_preinc(atomic_t *val)
     90NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
    8991{
    9092        return atomic_add(val, 1);
    … …  
    9799 *
    98100 */
    99 static inline atomic_count_t atomic_predec(atomic_t *val)
     101NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
    100102{
    101103        return atomic_add(val, -1);
    … …  
    108110 *
    109111 */
    110 static inline atomic_count_t atomic_postinc(atomic_t *val)
     112NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    111113{
    112114        return atomic_add(val, 1) - 1;
    … …  
    119121 *
    120122 */
    121 static inline atomic_count_t atomic_postdec(atomic_t *val)
     123NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    122124{
    123125        return atomic_add(val, -1) + 1;

  • kernel/arch/arm32/include/cycle.h

    re3ee9b9 r7a0359b  
    3737#define KERN_arm32_CYCLE_H_
    3838
    39 /** Returns count of CPU cycles.
     39#include <trace.h>
     40
     41/** Return count of CPU cycles.
    4042 *
    41  *  No such instruction on ARM to get count of cycles.
     43 * No such instruction on ARM to get count of cycles.
    4244 *
    43  *  @return Count of CPU cycles.
     45 * @return Count of CPU cycles.
     46 *
    4447 */
    45 static inline uint64_t get_cycle(void)
     48NO_TRACE static inline uint64_t get_cycle(void)
    4649{
    4750        return 0;

  • kernel/arch/arm32/include/exception.h

    re3ee9b9 r7a0359b  
    4040#include <typedefs.h>
    4141#include <arch/regutils.h>
     42#include <trace.h>
    4243
    4344/** If defined, forces using of high exception vectors. */
    … …  
    4546
    4647#ifdef HIGH_EXCEPTION_VECTORS
    47         #define EXC_BASE_ADDRESS        0xffff0000
     48        #define EXC_BASE_ADDRESS  0xffff0000
    4849#else
    49         #define EXC_BASE_ADDRESS        0x0
     50        #define EXC_BASE_ADDRESS  0x0
    5051#endif
    5152
    5253/* Exception Vectors */
    53 #define EXC_RESET_VEC          (EXC_BASE_ADDRESS + 0x0)
    54 #define EXC_UNDEF_INSTR_VEC    (EXC_BASE_ADDRESS + 0x4)
    55 #define EXC_SWI_VEC            (EXC_BASE_ADDRESS + 0x8)
    56 #define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc)
    57 #define EXC_DATA_ABORT_VEC     (EXC_BASE_ADDRESS + 0x10)
    58 #define EXC_IRQ_VEC            (EXC_BASE_ADDRESS + 0x18)
    59 #define EXC_FIQ_VEC            (EXC_BASE_ADDRESS + 0x1c)
     54#define EXC_RESET_VEC           (EXC_BASE_ADDRESS + 0x0)
     55#define EXC_UNDEF_INSTR_VEC     (EXC_BASE_ADDRESS + 0x4)
     56#define EXC_SWI_VEC             (EXC_BASE_ADDRESS + 0x8)
     57#define EXC_PREFETCH_ABORT_VEC  (EXC_BASE_ADDRESS + 0xc)
     58#define EXC_DATA_ABORT_VEC      (EXC_BASE_ADDRESS + 0x10)
     59#define EXC_IRQ_VEC             (EXC_BASE_ADDRESS + 0x18)
     60#define EXC_FIQ_VEC             (EXC_BASE_ADDRESS + 0x1c)
    6061
    6162/* Exception numbers */
    … …  
    6869#define EXC_FIQ             6
    6970
    70 
    7171/** Kernel stack pointer.
    7272 *
    7373 * It is set when thread switches to user mode,
    7474 * and then used for exception handling.
     75 *
    7576 */
    7677extern uintptr_t supervisor_sp;
    77 
    7878
    7979/** Temporary exception stack pointer.
    … …  
    8181 * Temporary stack is used in exceptions handling routines
    8282 * before switching to thread's kernel stack.
     83 *
    8384 */
    8485extern uintptr_t exc_stack;
    85 
    8686
    8787/** Struct representing CPU state saved when an exception occurs. */
    … …  
    9090        uint32_t sp;
    9191        uint32_t lr;
    92 
     92       
    9393        uint32_t r0;
    9494        uint32_t r1;
    … …  
    104104        uint32_t fp;
    105105        uint32_t r12;
    106 
     106       
    107107        uint32_t pc;
    108108} istate_t;
    109109
    110 
    111 /** Sets Program Counter member of given istate structure.
     110/** Set Program Counter member of given istate structure.
    112111 *
    113  * @param istate istate structure
     112 * @param istate  istate structure
    114113 * @param retaddr new value of istate's PC member
     114 *
    115115 */
    116 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     116NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     117    uintptr_t retaddr)
    117118{
    118         istate->pc = retaddr;
     119        istate->pc = retaddr;
    119120}
    120121
    121 
    122 /** Returns true if exception happened while in userspace. */
    123 static inline int istate_from_uspace(istate_t *istate)
     122/** Return true if exception happened while in userspace. */
     123NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    124124{
    125         return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
     125        return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
    126126}
    127127
    128 
    129 /** Returns Program Counter member of given istate structure. */
    130 static inline unative_t istate_get_pc(istate_t *istate)
     128/** Return Program Counter member of given istate structure. */
     129NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    131130{
    132         return istate->pc;
     131        return istate->pc;
    133132}
    134133
    135 static inline unative_t istate_get_fp(istate_t *istate)
     134NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    136135{
    137136        return istate->fp;
    138137}
    139 
    140138
    141139extern void install_exception_handlers(void);
    … …  
    149147extern void swi_exception_entry(void);
    150148
    151 
    152149#endif
    153150

  • kernel/arch/arm32/include/faddr.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup arm32   
     29/** @addtogroup arm32
    3030 * @{
    3131 */
    … …  
    4242 *
    4343 * @param fptr Function pointer.
     44 *
    4445 */
    45 #define FADDR(fptr)             ((uintptr_t) (fptr))
     46#define FADDR(fptr)  ((uintptr_t) (fptr))
    4647
    4748#endif

  • kernel/arch/arm32/include/interrupt.h

    re3ee9b9 r7a0359b  
    4141
    4242/** Initial size of exception dispatch table. */
    43 #define IVT_ITEMS       6
     43#define IVT_ITEMS  6
    4444
    4545/** Index of the first item in exception dispatch table. */
    46 #define IVT_FIRST       0
    47 
     46#define IVT_FIRST  0
    4847
    4948extern void interrupt_init(void);
    … …  
    5453extern bool interrupts_disabled(void);
    5554
    56 
    5755#endif
    5856

  • kernel/arch/arm32/include/mm/page.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */
    … …  
    4040#include <mm/mm.h>
    4141#include <arch/exception.h>
     42#include <trace.h>
    4243
    4344#define PAGE_WIDTH      FRAME_WIDTH
    … …  
    192193/** Sets the address of level 0 page table.
    193194 *
    194  * @param pt    Pointer to the page table to set.
    195  */   
    196 static inline void set_ptl0_addr(pte_t *pt)
     195 * @param pt Pointer to the page table to set.
     196 *
     197 */
     198NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    197199{
    198200        asm volatile (
    … …  
    205207/** Returns level 0 page table entry flags.
    206208 *
    207  *  @param pt     Level 0 page table.
    208  *  @param i      Index of the entry to return.
    209  */
    210 static inline int get_pt_level0_flags(pte_t *pt, size_t i)
     209 * @param pt Level 0 page table.
     210 * @param i  Index of the entry to return.
     211 *
     212 */
     213NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
    211214{
    212215        pte_level0_t *p = &pt[i].l0;
    213216        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    214 
     217       
    215218        return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
    216219            (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
    … …  
    220223/** Returns level 1 page table entry flags.
    221224 *
    222  *  @param pt     Level 1 page table.
    223  *  @param i      Index of the entry to return.
    224  */
    225 static inline int get_pt_level1_flags(pte_t *pt, size_t i)
     225 * @param pt Level 1 page table.
     226 * @param i  Index of the entry to return.
     227 *
     228 */
     229NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
    226230{
    227231        pte_level1_t *p = &pt[i].l1;
    228 
     232       
    229233        int dt = p->descriptor_type;
    230234        int ap = p->access_permission_0;
    231 
     235       
    232236        return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
    233237            ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
    … …  
    241245}
    242246
    243 
    244247/** Sets flags of level 0 page table entry.
    245248 *
    246  *  @param pt     level 0 page table
    247  *  @param i      index of the entry to be changed
    248  *  @param flags  new flags
    249  */
    250 static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
     249 * @param pt    level 0 page table
     250 * @param i     index of the entry to be changed
     251 * @param flags new flags
     252 *
     253 */
     254NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
    251255{
    252256        pte_level0_t *p = &pt[i].l0;
    253 
     257       
    254258        if (flags & PAGE_NOT_PRESENT) {
    255259                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    … …  
    262266                p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
    263267                p->should_be_zero = 0;
    264     }
     268        }
    265269}
    266270
    … …  
    268272/** Sets flags of level 1 page table entry.
    269273 *
    270  *  We use same access rights for the whole page. When page is not preset we
    271  *  store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
    272  *  page entry, see #PAGE_VALID_ARCH).
    273  *
    274  *  @param pt     Level 1 page table.
    275  *  @param i      Index of the entry to be changed.
    276  *  @param flags  New flags.
    277  */ 
    278 static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
     274 * We use same access rights for the whole page. When page
     275 * is not preset we store 1 in acess_rigts_3 so that at least
     276 * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
     277 *
     278 * @param pt    Level 1 page table.
     279 * @param i     Index of the entry to be changed.
     280 * @param flags New flags.
     281 *
     282 */
     283NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
    279284{
    280285        pte_level1_t *p = &pt[i].l1;
    … …  
    287292                p->access_permission_3 = p->access_permission_0;
    288293        }
    289  
     294       
    290295        p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
    291 
     296       
    292297        /* default access permission */
    293298        p->access_permission_0 = p->access_permission_1 =
    294299            p->access_permission_2 = p->access_permission_3 =
    295300            PTE_AP_USER_NO_KERNEL_RW;
    296 
     301       
    297302        if (flags & PAGE_USER)  {
    298303                if (flags & PAGE_READ) {

  • kernel/arch/arm32/include/mm/tlb.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */
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