Changes in kernel/arch/amd64/include/atomic.h [c00589d:7a0359b] in mainline

File:

• kernel/arch/amd64/include/atomic.h (modified) (6 diffs)

kernel/arch/amd64/include/atomic.h

@@ -36 +36 @@
 #define KERN_amd64_ATOMIC_H_
 
-#include <arch/types.h>
+#include <typedefs.h>
 #include <arch/barrier.h>
 #include <preemption.h>
+#include <trace.h>
 
-static inline void atomic_inc(atomic_t *val) {
+NO_TRACE static inline void atomic_inc(atomic_t *val)
+{
 #ifdef CONFIG_SMP
         asm volatile (
@@ -54 +56 @@
 }
 
-static inline void atomic_dec(atomic_t *val) {
+NO_TRACE static inline void atomic_dec(atomic_t *val)
+{
 #ifdef CONFIG_SMP
         asm volatile (
@@ -68 +71 @@
 }
 
-static inline long atomic_postinc(atomic_t *val) 
+NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
 {
-        long r = 1;
+        atomic_count_t r = 1;
         
         asm volatile (
                 "lock xaddq %[r], %[count]\n"
-                : [count] "+m" (val->count), [r] "+r" (r)
+                : [count] "+m" (val->count),
+                  [r] "+r" (r)
         );
         
@@ -80 +84 @@
 }
 
-static inline long atomic_postdec(atomic_t *val) 
+NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
 {
-        long r = -1;
+        atomic_count_t r = -1;
         
         asm volatile (
                 "lock xaddq %[r], %[count]\n"
-                : [count] "+m" (val->count), [r] "+r" (r)
+                : [count] "+m" (val->count),
+                  [r] "+r" (r)
         );
         
@@ -95 +100 @@
 #define atomic_predec(val)  (atomic_postdec(val) - 1)
 
-static inline uint64_t test_and_set(atomic_t *val) {
-        uint64_t v;
+NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
+{
+        atomic_count_t v = 1;
         
         asm volatile (
-                "movq $1, %[v]\n"
                 "xchgq %[v], %[count]\n"
-                : [v] "=r" (v), [count] "+m" (val->count)
+                : [v] "+r" (v),
+                  [count] "+m" (val->count)
         );
         
@@ -107 +113 @@
 }
 
-
 /** amd64 specific fast spinlock */
-static inline void atomic_lock_arch(atomic_t *val)
+NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
 {
-        uint64_t tmp;
+        atomic_count_t tmp;
         
         preemption_disable();
         asm volatile (
                 "0:\n"
-                "pause\n"
-                "mov %[count], %[tmp]\n"
-                "testq %[tmp], %[tmp]\n"
-                "jnz 0b\n"       /* lightweight looping on locked spinlock */
+                "       pause\n"
+                "       mov %[count], %[tmp]\n"
+                "       testq %[tmp], %[tmp]\n"
+                "       jnz 0b\n"       /* lightweight looping on locked spinlock */
                 
-                "incq %[tmp]\n"  /* now use the atomic operation */
-                "xchgq %[count], %[tmp]\n"
-                "testq %[tmp], %[tmp]\n"
-                "jnz 0b\n"
-                : [count] "+m" (val->count), [tmp] "=&r" (tmp)
+                "       incq %[tmp]\n"  /* now use the atomic operation */
+                "       xchgq %[count], %[tmp]\n"
+                "       testq %[tmp], %[tmp]\n"
+                "       jnz 0b\n"
+                : [count] "+m" (val->count),
+                  [tmp] "=&r" (tmp)
         );
+        
         /*
          * Prevent critical section code from bleeding out this way up.