Changeset 7a0359b in mainline for kernel/arch


Ignore:
Timestamp:
2010-07-02T15:42:19Z (15 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bbfdf62
Parents:
e3ee9b9
Message:

improve kernel function tracing

  • add support for more generic kernel sources
  • replace attribute((no_instrument_function)) with NO_TRACE macro (shorter and for future compatibility with different compilers)
  • to be on the safe side, do not instrument most of the inline and static functions (plus some specific non-static functions)

collateral code cleanup (no change in functionality)

Location:
kernel/arch
Files:
62 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/include/asm.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <config.h>
    40 
    41 static inline void asm_delay_loop(uint32_t usec)
    42 {
    43 }
    44 
    45 static inline __attribute__((noreturn)) void cpu_halt(void)
     40#include <trace.h>
     41
     42NO_TRACE static inline void asm_delay_loop(uint32_t usec)
     43{
     44}
     45
     46NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
    4647{
    4748        /* On real hardware this should stop processing further
    … …  
    5354}
    5455
    55 static inline void cpu_sleep(void)
     56NO_TRACE static inline void cpu_sleep(void)
    5657{
    5758        /* On real hardware this should put the CPU into low-power
    … …  
    6162}
    6263
    63 static inline void pio_write_8(ioport8_t *port, uint8_t val)
     64NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
    6465{
    6566}
    … …  
    7374 *
    7475 */
    75 static inline void pio_write_16(ioport16_t *port, uint16_t val)
     76NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
    7677{
    7778}
    … …  
    8586 *
    8687 */
    87 static inline void pio_write_32(ioport32_t *port, uint32_t val)
     88NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
    8889{
    8990}
    … …  
    9798 *
    9899 */
    99 static inline uint8_t pio_read_8(ioport8_t *port)
     100NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    100101{
    101102        return 0;
    … …  
    110111 *
    111112 */
    112 static inline uint16_t pio_read_16(ioport16_t *port)
     113NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    113114{
    114115        return 0;
    … …  
    123124 *
    124125 */
    125 static inline uint32_t pio_read_32(ioport32_t *port)
    126 {
    127         return 0;
    128 }
    129 
    130 static inline ipl_t interrupts_enable(void)
    131 {
    132         /* On real hardware this unconditionally enables preemption
    133            by internal and external interrupts.
    134            
    135            The return value stores the previous interrupt level. */
    136        
    137         return 0;
    138 }
    139 
    140 static inline ipl_t interrupts_disable(void)
    141 {
    142         /* On real hardware this disables preemption by the usual
    143            set of internal and external interrupts. This does not
    144            apply to special non-maskable interrupts and sychronous
    145            CPU exceptions.
    146            
    147            The return value stores the previous interrupt level. */
    148        
    149         return 0;
    150 }
    151 
    152 static inline void interrupts_restore(ipl_t ipl)
    153 {
    154         /* On real hardware this either enables or disables preemption
    155            according to the interrupt level value from the argument. */
    156 }
    157 
    158 static inline ipl_t interrupts_read(void)
    159 {
    160         /* On real hardware the return value stores the current interrupt
    161            level. */
    162        
    163         return 0;
    164 }
    165 
    166 static inline bool interrupts_disabled(void)
    167 {
    168         /* On real hardware the return value is true iff interrupts are
    169            disabled. */
     126NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
     127{
     128        return 0;
     129}
     130
     131NO_TRACE static inline ipl_t interrupts_enable(void)
     132{
     133        /*
     134         * On real hardware this unconditionally enables preemption
     135         * by internal and external interrupts.
     136         *
     137         * The return value stores the previous interrupt level.
     138         */
     139       
     140        return 0;
     141}
     142
     143NO_TRACE static inline ipl_t interrupts_disable(void)
     144{
     145        /*
     146         * On real hardware this disables preemption by the usual
     147         * set of internal and external interrupts. This does not
     148         * apply to special non-maskable interrupts and sychronous
     149         * CPU exceptions.
     150         *
     151         * The return value stores the previous interrupt level.
     152         */
     153       
     154        return 0;
     155}
     156
     157NO_TRACE static inline void interrupts_restore(ipl_t ipl)
     158{
     159        /*
     160         * On real hardware this either enables or disables preemption
     161         * according to the interrupt level value from the argument.
     162         */
     163}
     164
     165NO_TRACE static inline ipl_t interrupts_read(void)
     166{
     167        /*
     168         * On real hardware the return value stores the current interrupt
     169         * level.
     170         */
     171       
     172        return 0;
     173}
     174
     175NO_TRACE static inline bool interrupts_disabled(void)
     176{
     177        /*
     178         * On real hardware the return value is true iff interrupts are
     179         * disabled.
     180         */
     181       
    170182        return false;
    171183}
    172184
    173 static inline uintptr_t get_stack_base(void)
    174 {
    175         /* On real hardware this returns the address of the bottom
    176            of the current CPU stack. The the_t structure is stored
    177            on the bottom of stack and this is used to identify the
    178            current CPU, current task, current thread and current
    179            address space. */
     185NO_TRACE static inline uintptr_t get_stack_base(void)
     186{
     187        /*
     188         * On real hardware this returns the address of the bottom
     189         * of the current CPU stack. The the_t structure is stored
     190         * on the bottom of stack and this is used to identify the
     191         * current CPU, current task, current thread and current
     192         * address space.
     193         */
    180194       
    181195        return 0;

  • kernel/arch/abs32le/include/atomic.h

    re3ee9b9 r7a0359b  
    4040#include <preemption.h>
    4141#include <verify.h>
     42#include <trace.h>
    4243
    43 ATOMIC static inline void atomic_inc(atomic_t *val)
     44NO_TRACE ATOMIC static inline void atomic_inc(atomic_t *val)
    4445    WRITES(&val->count)
    4546    REQUIRES_EXTENT_MUTABLE(val)
    … …  
    5253}
    5354
    54 ATOMIC static inline void atomic_dec(atomic_t *val)
     55NO_TRACE ATOMIC static inline void atomic_dec(atomic_t *val)
    5556    WRITES(&val->count)
    5657    REQUIRES_EXTENT_MUTABLE(val)
    … …  
    6364}
    6465
    65 ATOMIC static inline atomic_count_t atomic_postinc(atomic_t *val)
     66NO_TRACE ATOMIC static inline atomic_count_t atomic_postinc(atomic_t *val)
    6667    WRITES(&val->count)
    6768    REQUIRES_EXTENT_MUTABLE(val)
    … …  
    7879}
    7980
    80 ATOMIC static inline atomic_count_t atomic_postdec(atomic_t *val)
     81NO_TRACE ATOMIC static inline atomic_count_t atomic_postdec(atomic_t *val)
    8182    WRITES(&val->count)
    8283    REQUIRES_EXTENT_MUTABLE(val)
    … …  
    9697#define atomic_predec(val)  (atomic_postdec(val) - 1)
    9798
    98 ATOMIC static inline atomic_count_t test_and_set(atomic_t *val)
     99NO_TRACE ATOMIC static inline atomic_count_t test_and_set(atomic_t *val)
    99100    WRITES(&val->count)
    100101    REQUIRES_EXTENT_MUTABLE(val)
    … …  
    109110}
    110111
    111 static inline void atomic_lock_arch(atomic_t *val)
     112NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    112113    WRITES(&val->count)
    113114    REQUIRES_EXTENT_MUTABLE(val)

  • kernel/arch/abs32le/include/cycle.h

    re3ee9b9 r7a0359b  
    3636#define KERN_abs32le_CYCLE_H_
    3737
    38 static inline uint64_t get_cycle(void)
     38#include <trace.h>
     39
     40NO_TRACE static inline uint64_t get_cycle(void)
    3941{
    4042        return 0;

  • kernel/arch/abs32le/include/interrupt.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <verify.h>
     40#include <trace.h>
    4041
    4142#define IVT_ITEMS  0
    … …  
    5455} istate_t;
    5556
    56 static inline int istate_from_uspace(istate_t *istate)
     57NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    5758    REQUIRES_EXTENT_MUTABLE(istate)
    5859{
    … …  
    6364}
    6465
    65 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     66NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     67    uintptr_t retaddr)
    6668    WRITES(&istate->ip)
    6769{
    … …  
    7173}
    7274
    73 static inline unative_t istate_get_pc(istate_t *istate)
     75NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    7476    REQUIRES_EXTENT_MUTABLE(istate)
    7577{
    … …  
    7981}
    8082
    81 static inline unative_t istate_get_fp(istate_t *istate)
     83NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    8284    REQUIRES_EXTENT_MUTABLE(istate)
    8385{

  • kernel/arch/abs32le/include/mm/page.h

    re3ee9b9 r7a0359b  
    3737
    3838#include <arch/mm/frame.h>
     39#include <trace.h>
    3940
    4041#define PAGE_WIDTH  FRAME_WIDTH
    … …  
    139140} __attribute__((packed)) pte_t;
    140141
    141 static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     142NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    142143    REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH)
    143144{
    … …  
    155156}
    156157
    157 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     158NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    158159    WRITES(ARRAY_RANGE(pt, PTL0_ENTRIES_ARCH))
    159160    REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH)

  • kernel/arch/amd64/include/asm.h

    re3ee9b9 r7a0359b  
    3939#include <typedefs.h>
    4040#include <arch/cpu.h>
    41 
    42 extern void asm_delay_loop(uint32_t t);
    43 extern void asm_fake_loop(uint32_t t);
     41#include <trace.h>
    4442
    4543/** Return base address of current stack.
    … …  
    5048 *
    5149 */
    52 static inline uintptr_t get_stack_base(void)
     50NO_TRACE static inline uintptr_t get_stack_base(void)
    5351{
    5452        uintptr_t v;
    … …  
    5755                "andq %%rsp, %[v]\n"
    5856                : [v] "=r" (v)
    59                 : "0" (~((uint64_t) STACK_SIZE-1))
     57                : "0" (~((uint64_t) STACK_SIZE - 1))
    6058        );
    6159       
    … …  
    6361}
    6462
    65 static inline void cpu_sleep(void)
    66 {
    67         asm volatile ("hlt\n");
    68 }
    69 
    70 static inline void __attribute__((noreturn)) cpu_halt(void)
     63NO_TRACE static inline void cpu_sleep(void)
     64{
     65        asm volatile (
     66                "hlt\n"
     67        );
     68}
     69
     70NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
    7171{
    7272        while (true) {
    … …  
    7777}
    7878
    79 
    8079/** Byte from port
    8180 *
    … …  
    8685 *
    8786 */
    88 static inline uint8_t pio_read_8(ioport8_t *port)
     87NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    8988{
    9089        uint8_t val;
    … …  
    107106 *
    108107 */
    109 static inline uint16_t pio_read_16(ioport16_t *port)
     108NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    110109{
    111110        uint16_t val;
    … …  
    128127 *
    129128 */
    130 static inline uint32_t pio_read_32(ioport32_t *port)
     129NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    131130{
    132131        uint32_t val;
    … …  
    149148 *
    150149 */
    151 static inline void pio_write_8(ioport8_t *port, uint8_t val)
     150NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
    152151{
    153152        asm volatile (
    154153                "outb %b[val], %w[port]\n"
    155                 :: [val] "a" (val), [port] "d" (port)
     154                :: [val] "a" (val),
     155                   [port] "d" (port)
    156156        );
    157157}
    … …  
    165165 *
    166166 */
    167 static inline void pio_write_16(ioport16_t *port, uint16_t val)
     167NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
    168168{
    169169        asm volatile (
    170170                "outw %w[val], %w[port]\n"
    171                 :: [val] "a" (val), [port] "d" (port)
     171                :: [val] "a" (val),
     172                   [port] "d" (port)
    172173        );
    173174}
    … …  
    181182 *
    182183 */
    183 static inline void pio_write_32(ioport32_t *port, uint32_t val)
     184NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
    184185{
    185186        asm volatile (
    186187                "outl %[val], %w[port]\n"
    187                 :: [val] "a" (val), [port] "d" (port)
     188                :: [val] "a" (val),
     189                   [port] "d" (port)
    188190        );
    189191}
    190192
    191193/** Swap Hidden part of GS register with visible one */
    192 static inline void swapgs(void)
    193 {
    194         asm volatile("swapgs");
     194NO_TRACE static inline void swapgs(void)
     195{
     196        asm volatile (
     197                "swapgs"
     198        );
    195199}
    196200
    … …  
    203207 *
    204208 */
    205 static inline ipl_t interrupts_enable(void) {
     209NO_TRACE static inline ipl_t interrupts_enable(void) {
    206210        ipl_t v;
    207211       
    … …  
    224228 *
    225229 */
    226 static inline ipl_t interrupts_disable(void) {
     230NO_TRACE static inline ipl_t interrupts_disable(void) {
    227231        ipl_t v;
    228232       
    … …  
    244248 *
    245249 */
    246 static inline void interrupts_restore(ipl_t ipl) {
     250NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
    247251        asm volatile (
    248252                "pushq %[ipl]\n"
    … …  
    259263 *
    260264 */
    261 static inline ipl_t interrupts_read(void) {
     265NO_TRACE static inline ipl_t interrupts_read(void) {
    262266        ipl_t v;
    263267       
    … …  
    276280 *
    277281 */
    278 static inline bool interrupts_disabled(void)
     282NO_TRACE static inline bool interrupts_disabled(void)
    279283{
    280284        ipl_t v;
    … …  
    289293}
    290294
    291 
    292295/** Write to MSR */
    293 static inline void write_msr(uint32_t msr, uint64_t value)
     296NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
    294297{
    295298        asm volatile (
    … …  
    301304}
    302305
    303 static inline unative_t read_msr(uint32_t msr)
     306NO_TRACE static inline unative_t read_msr(uint32_t msr)
    304307{
    305308        uint32_t ax, dx;
    … …  
    314317}
    315318
    316 
    317319/** Enable local APIC
    318320 *
    … …  
    320322 *
    321323 */
    322 static inline void enable_l_apic_in_msr()
     324NO_TRACE static inline void enable_l_apic_in_msr()
    323325{
    324326        asm volatile (
    … …  
    328330                "orl $(0xfee00000),%%eax\n"
    329331                "wrmsr\n"
    330                 ::: "%eax","%ecx","%edx"
     332                ::: "%eax", "%ecx", "%edx"
    331333        );
    332334}
    … …  
    337339 *
    338340 */
    339 static inline void invlpg(uintptr_t addr)
     341NO_TRACE static inline void invlpg(uintptr_t addr)
    340342{
    341343        asm volatile (
    … …  
    350352 *
    351353 */
    352 static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
     354NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
    353355{
    354356        asm volatile (
    … …  
    363365 *
    364366 */
    365 static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
     367NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
    366368{
    367369        asm volatile (
    … …  
    376378 *
    377379 */
    378 static inline void idtr_load(ptr_16_64_t *idtr_reg)
     380NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
    379381{
    380382        asm volatile (
    … …  
    388390 *
    389391 */
    390 static inline void tr_load(uint16_t sel)
     392NO_TRACE static inline void tr_load(uint16_t sel)
    391393{
    392394        asm volatile (
    … …  
    396398}
    397399
    398 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     400#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
    399401        { \
    400402                unative_t res; \
    … …  
    406408        }
    407409
    408 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     410#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
    409411        { \
    410412                asm volatile ( \
    … …  
    436438extern void interrupt_handlers(void);
    437439
     440extern void asm_delay_loop(uint32_t);
     441extern void asm_fake_loop(uint32_t);
     442
    438443#endif
    439444

  • kernel/arch/amd64/include/atomic.h

    re3ee9b9 r7a0359b  
    3939#include <arch/barrier.h>
    4040#include <preemption.h>
     41#include <trace.h>
    4142
    42 static inline void atomic_inc(atomic_t *val)
     43NO_TRACE static inline void atomic_inc(atomic_t *val)
    4344{
    4445#ifdef CONFIG_SMP
    … …  
    5556}
    5657
    57 static inline void atomic_dec(atomic_t *val)
     58NO_TRACE static inline void atomic_dec(atomic_t *val)
    5859{
    5960#ifdef CONFIG_SMP
    … …  
    7071}
    7172
    72 static inline atomic_count_t atomic_postinc(atomic_t *val)
     73NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    7374{
    7475        atomic_count_t r = 1;
    … …  
    8384}
    8485
    85 static inline atomic_count_t atomic_postdec(atomic_t *val)
     86NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    8687{
    8788        atomic_count_t r = -1;
    … …  
    99100#define atomic_predec(val)  (atomic_postdec(val) - 1)
    100101
    101 static inline atomic_count_t test_and_set(atomic_t *val)
     102NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
    102103{
    103104        atomic_count_t v = 1;
    … …  
    113114
    114115/** amd64 specific fast spinlock */
    115 static inline void atomic_lock_arch(atomic_t *val)
     116NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    116117{
    117118        atomic_count_t tmp;
    … …  
    120121        asm volatile (
    121122                "0:\n"
    122                 "pause\n"
    123                 "mov %[count], %[tmp]\n"
    124                 "testq %[tmp], %[tmp]\n"
    125                 "jnz 0b\n"       /* lightweight looping on locked spinlock */
     123                "       pause\n"
     124                "       mov %[count], %[tmp]\n"
     125                "       testq %[tmp], %[tmp]\n"
     126                "       jnz 0b\n"       /* lightweight looping on locked spinlock */
    126127               
    127                 "incq %[tmp]\n"  /* now use the atomic operation */
    128                 "xchgq %[count], %[tmp]\n"
    129                 "testq %[tmp], %[tmp]\n"
    130                 "jnz 0b\n"
     128                "       incq %[tmp]\n"  /* now use the atomic operation */
     129                "       xchgq %[count], %[tmp]\n"
     130                "       testq %[tmp], %[tmp]\n"
     131                "       jnz 0b\n"
    131132                : [count] "+m" (val->count),
    132133                  [tmp] "=&r" (tmp)

  • kernel/arch/amd64/include/cycle.h

    re3ee9b9 r7a0359b  
    3636#define KERN_amd64_CYCLE_H_
    3737
    38 static inline uint64_t get_cycle(void)
     38#include <trace.h>
     39
     40NO_TRACE static inline uint64_t get_cycle(void)
    3941{
    4042        uint32_t lower;

  • kernel/arch/amd64/include/interrupt.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <arch/pm.h>
     40#include <trace.h>
    4041
    41 #define IVT_ITEMS               IDT_ITEMS
    42 #define IVT_FIRST               0
     42#define IVT_ITEMS  IDT_ITEMS
     43#define IVT_FIRST  0
    4344
    44 #define EXC_COUNT               32
    45 #define IRQ_COUNT               16
     45#define EXC_COUNT  32
     46#define IRQ_COUNT  16
    4647
    47 #define IVT_EXCBASE             0
    48 #define IVT_IRQBASE             (IVT_EXCBASE + EXC_COUNT)
    49 #define IVT_FREEBASE            (IVT_IRQBASE + IRQ_COUNT)
     48#define IVT_EXCBASE   0
     49#define IVT_IRQBASE   (IVT_EXCBASE + EXC_COUNT)
     50#define IVT_FREEBASE  (IVT_IRQBASE + IRQ_COUNT)
    5051
    51 #define IRQ_CLK                 0
    52 #define IRQ_KBD                 1
    53 #define IRQ_PIC1                2
    54 #define IRQ_PIC_SPUR            7
    55 #define IRQ_MOUSE               12
    56 #define IRQ_DP8390              9
     52#define IRQ_CLK       0
     53#define IRQ_KBD       1
     54#define IRQ_PIC1      2
     55#define IRQ_PIC_SPUR  7
     56#define IRQ_MOUSE     12
     57#define IRQ_DP8390    9
    5758
    58 /* this one must have four least significant bits set to ones */
    59 #define VECTOR_APIC_SPUR        (IVT_ITEMS - 1)
     59/* This one must have four least significant bits set to ones */
     60#define VECTOR_APIC_SPUR  (IVT_ITEMS - 1)
    6061
    6162#if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
    … …  
    6364#endif
    6465
    65 #define VECTOR_DEBUG                    1
    66 #define VECTOR_CLK                      (IVT_IRQBASE + IRQ_CLK)
    67 #define VECTOR_PIC_SPUR                 (IVT_IRQBASE + IRQ_PIC_SPUR)
    68 #define VECTOR_SYSCALL                  IVT_FREEBASE
    69 #define VECTOR_TLB_SHOOTDOWN_IPI        (IVT_FREEBASE + 1)
    70 #define VECTOR_DEBUG_IPI                (IVT_FREEBASE + 2)
     66#define VECTOR_DEBUG              1
     67#define VECTOR_CLK                (IVT_IRQBASE + IRQ_CLK)
     68#define VECTOR_PIC_SPUR           (IVT_IRQBASE + IRQ_PIC_SPUR)
     69#define VECTOR_SYSCALL            IVT_FREEBASE
     70#define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
     71#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
    7172
    7273/** This is passed to interrupt handlers */
    … …  
    8687        uint64_t cs;
    8788        uint64_t rflags;
    88         uint64_t stack[]; /* Additional data on stack */
     89        uint64_t stack[];  /* Additional data on stack */
    8990} istate_t;
    9091
    9192/** Return true if exception happened while in userspace */
    92 static inline int istate_from_uspace(istate_t *istate)
     93NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    9394{
    9495        return !(istate->rip & 0x8000000000000000);
    9596}
    9697
    97 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     98NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     99    uintptr_t retaddr)
    98100{
    99101        istate->rip = retaddr;
    100102}
    101 static inline unative_t istate_get_pc(istate_t *istate)
     103
     104NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    102105{
    103106        return istate->rip;
    104107}
    105 static inline unative_t istate_get_fp(istate_t *istate)
     108
     109NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    106110{
    107111        return istate->rbp;
    108112}
    109113
    110 extern void (* disable_irqs_function)(uint16_t irqmask);
    111 extern void (* enable_irqs_function)(uint16_t irqmask);
     114extern void (* disable_irqs_function)(uint16_t);
     115extern void (* enable_irqs_function)(uint16_t);
    112116extern void (* eoi_function)(void);
    113117
    114118extern void interrupt_init(void);
    115 extern void trap_virtual_enable_irqs(uint16_t irqmask);
    116 extern void trap_virtual_disable_irqs(uint16_t irqmask);
     119extern void trap_virtual_enable_irqs(uint16_t);
     120extern void trap_virtual_disable_irqs(uint16_t);
    117121
    118122#endif

  • kernel/arch/amd64/include/mm/frame.h

    re3ee9b9 r7a0359b  
    3636#define KERN_amd64_FRAME_H_
    3737
    38 #ifndef __ASM__
    39 #include <typedefs.h>
    40 #endif /* __ASM__ */
    41 
    4238#define FRAME_WIDTH  12  /* 4K */
    4339#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4440
     41#ifdef KERNEL
    4542#ifndef __ASM__
     43
     44#include <typedefs.h>
     45
    4646extern uintptr_t last_frame;
    4747extern void frame_arch_init(void);
    4848extern void physmem_print(void);
     49
    4950#endif /* __ASM__ */
     51#endif /* KERNEL */
    5052
    5153#endif

  • kernel/arch/amd64/include/mm/page.h

    re3ee9b9 r7a0359b  
    4646
    4747#include <arch/mm/frame.h>
     48#include <trace.h>
    4849
    4950#define PAGE_WIDTH  FRAME_WIDTH
    … …  
    187188} __attribute__ ((packed)) pte_t;
    188189
    189 static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     190NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    190191{
    191192        pte_t *p = &pt[i];
    … …  
    200201}
    201202
    202 static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
     203NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
    203204{
    204205        pte_t *p = &pt[i];
    … …  
    208209}
    209210
    210 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     211NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    211212{
    212213        pte_t *p = &pt[i];

  • kernel/arch/arm32/include/asm.h

    re3ee9b9 r7a0359b  
    4141#include <config.h>
    4242#include <arch/interrupt.h>
     43#include <trace.h>
    4344
    4445/** No such instruction on ARM to sleep CPU. */
    45 static inline void cpu_sleep(void)
     46NO_TRACE static inline void cpu_sleep(void)
    4647{
    4748}
    4849
    49 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     50NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    5051{
    5152        *port = v;
    5253}
    5354
    54 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     55NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    5556{
    5657        *port = v;
    5758}
    5859
    59 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     60NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    6061{
    6162        *port = v;
    6263}
    6364
    64 static inline uint8_t pio_read_8(ioport8_t *port)
     65NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    6566{
    6667        return *port;
    6768}
    6869
    69 static inline uint16_t pio_read_16(ioport16_t *port)
     70NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    7071{
    7172        return *port;
    7273}
    7374
    74 static inline uint32_t pio_read_32(ioport32_t *port)
     75NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    7576{
    7677        return *port;
    … …  
    8485 *
    8586 */
    86 static inline uintptr_t get_stack_base(void)
     87NO_TRACE static inline uintptr_t get_stack_base(void)
    8788{
    8889        uintptr_t v;
     90       
    8991        asm volatile (
    9092                "and %[v], sp, %[size]\n"
    … …  
    9294                : [size] "r" (~(STACK_SIZE - 1))
    9395        );
     96       
    9497        return v;
    9598}

  • kernel/arch/arm32/include/atomic.h

    re3ee9b9 r7a0359b  
    3838
    3939#include <arch/asm.h>
     40#include <trace.h>
    4041
    4142/** Atomic addition.
    … …  
    4748 *
    4849 */
    49 static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
     50NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
     51    atomic_count_t i)
    5052{
    5153        /*
    … …  
    6668 *
    6769 */
    68 static inline void atomic_inc(atomic_t *val)
     70NO_TRACE static inline void atomic_inc(atomic_t *val)
    6971{
    7072        atomic_add(val, 1);
    … …  
    7678 *
    7779 */
    78 static inline void atomic_dec(atomic_t *val) {
     80NO_TRACE static inline void atomic_dec(atomic_t *val) {
    7981        atomic_add(val, -1);
    8082}
    … …  
    8688 *
    8789 */
    88 static inline atomic_count_t atomic_preinc(atomic_t *val)
     90NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
    8991{
    9092        return atomic_add(val, 1);
    … …  
    9799 *
    98100 */
    99 static inline atomic_count_t atomic_predec(atomic_t *val)
     101NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
    100102{
    101103        return atomic_add(val, -1);
    … …  
    108110 *
    109111 */
    110 static inline atomic_count_t atomic_postinc(atomic_t *val)
     112NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    111113{
    112114        return atomic_add(val, 1) - 1;
    … …  
    119121 *
    120122 */
    121 static inline atomic_count_t atomic_postdec(atomic_t *val)
     123NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    122124{
    123125        return atomic_add(val, -1) + 1;

  • kernel/arch/arm32/include/cycle.h

    re3ee9b9 r7a0359b  
    3737#define KERN_arm32_CYCLE_H_
    3838
    39 /** Returns count of CPU cycles.
     39#include <trace.h>
     40
     41/** Return count of CPU cycles.
    4042 *
    41  *  No such instruction on ARM to get count of cycles.
     43 * No such instruction on ARM to get count of cycles.
    4244 *
    43  *  @return Count of CPU cycles.
     45 * @return Count of CPU cycles.
     46 *
    4447 */
    45 static inline uint64_t get_cycle(void)
     48NO_TRACE static inline uint64_t get_cycle(void)
    4649{
    4750        return 0;

  • kernel/arch/arm32/include/exception.h

    re3ee9b9 r7a0359b  
    4040#include <typedefs.h>
    4141#include <arch/regutils.h>
     42#include <trace.h>
    4243
    4344/** If defined, forces using of high exception vectors. */
    … …  
    4546
    4647#ifdef HIGH_EXCEPTION_VECTORS
    47         #define EXC_BASE_ADDRESS        0xffff0000
     48        #define EXC_BASE_ADDRESS  0xffff0000
    4849#else
    49         #define EXC_BASE_ADDRESS        0x0
     50        #define EXC_BASE_ADDRESS  0x0
    5051#endif
    5152
    5253/* Exception Vectors */
    53 #define EXC_RESET_VEC          (EXC_BASE_ADDRESS + 0x0)
    54 #define EXC_UNDEF_INSTR_VEC    (EXC_BASE_ADDRESS + 0x4)
    55 #define EXC_SWI_VEC            (EXC_BASE_ADDRESS + 0x8)
    56 #define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc)
    57 #define EXC_DATA_ABORT_VEC     (EXC_BASE_ADDRESS + 0x10)
    58 #define EXC_IRQ_VEC            (EXC_BASE_ADDRESS + 0x18)
    59 #define EXC_FIQ_VEC            (EXC_BASE_ADDRESS + 0x1c)
     54#define EXC_RESET_VEC           (EXC_BASE_ADDRESS + 0x0)
     55#define EXC_UNDEF_INSTR_VEC     (EXC_BASE_ADDRESS + 0x4)
     56#define EXC_SWI_VEC             (EXC_BASE_ADDRESS + 0x8)
     57#define EXC_PREFETCH_ABORT_VEC  (EXC_BASE_ADDRESS + 0xc)
     58#define EXC_DATA_ABORT_VEC      (EXC_BASE_ADDRESS + 0x10)
     59#define EXC_IRQ_VEC             (EXC_BASE_ADDRESS + 0x18)
     60#define EXC_FIQ_VEC             (EXC_BASE_ADDRESS + 0x1c)
    6061
    6162/* Exception numbers */
    … …  
    6869#define EXC_FIQ             6
    6970
    70 
    7171/** Kernel stack pointer.
    7272 *
    7373 * It is set when thread switches to user mode,
    7474 * and then used for exception handling.
     75 *
    7576 */
    7677extern uintptr_t supervisor_sp;
    77 
    7878
    7979/** Temporary exception stack pointer.
    … …  
    8181 * Temporary stack is used in exceptions handling routines
    8282 * before switching to thread's kernel stack.
     83 *
    8384 */
    8485extern uintptr_t exc_stack;
    85 
    8686
    8787/** Struct representing CPU state saved when an exception occurs. */
    … …  
    9090        uint32_t sp;
    9191        uint32_t lr;
    92 
     92       
    9393        uint32_t r0;
    9494        uint32_t r1;
    … …  
    104104        uint32_t fp;
    105105        uint32_t r12;
    106 
     106       
    107107        uint32_t pc;
    108108} istate_t;
    109109
    110 
    111 /** Sets Program Counter member of given istate structure.
     110/** Set Program Counter member of given istate structure.
    112111 *
    113  * @param istate istate structure
     112 * @param istate  istate structure
    114113 * @param retaddr new value of istate's PC member
     114 *
    115115 */
    116 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     116NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     117    uintptr_t retaddr)
    117118{
    118         istate->pc = retaddr;
     119        istate->pc = retaddr;
    119120}
    120121
    121 
    122 /** Returns true if exception happened while in userspace. */
    123 static inline int istate_from_uspace(istate_t *istate)
     122/** Return true if exception happened while in userspace. */
     123NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    124124{
    125         return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
     125        return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
    126126}
    127127
    128 
    129 /** Returns Program Counter member of given istate structure. */
    130 static inline unative_t istate_get_pc(istate_t *istate)
     128/** Return Program Counter member of given istate structure. */
     129NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    131130{
    132         return istate->pc;
     131        return istate->pc;
    133132}
    134133
    135 static inline unative_t istate_get_fp(istate_t *istate)
     134NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    136135{
    137136        return istate->fp;
    138137}
    139 
    140138
    141139extern void install_exception_handlers(void);
    … …  
    149147extern void swi_exception_entry(void);
    150148
    151 
    152149#endif
    153150

  • kernel/arch/arm32/include/faddr.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup arm32   
     29/** @addtogroup arm32
    3030 * @{
    3131 */
    … …  
    4242 *
    4343 * @param fptr Function pointer.
     44 *
    4445 */
    45 #define FADDR(fptr)             ((uintptr_t) (fptr))
     46#define FADDR(fptr)  ((uintptr_t) (fptr))
    4647
    4748#endif

  • kernel/arch/arm32/include/interrupt.h

    re3ee9b9 r7a0359b  
    4141
    4242/** Initial size of exception dispatch table. */
    43 #define IVT_ITEMS       6
     43#define IVT_ITEMS  6
    4444
    4545/** Index of the first item in exception dispatch table. */
    46 #define IVT_FIRST       0
    47 
     46#define IVT_FIRST  0
    4847
    4948extern void interrupt_init(void);
    … …  
    5453extern bool interrupts_disabled(void);
    5554
    56 
    5755#endif
    5856

  • kernel/arch/arm32/include/mm/page.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */
    … …  
    4040#include <mm/mm.h>
    4141#include <arch/exception.h>
     42#include <trace.h>
    4243
    4344#define PAGE_WIDTH      FRAME_WIDTH
    … …  
    192193/** Sets the address of level 0 page table.
    193194 *
    194  * @param pt    Pointer to the page table to set.
    195  */   
    196 static inline void set_ptl0_addr(pte_t *pt)
     195 * @param pt Pointer to the page table to set.
     196 *
     197 */
     198NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    197199{
    198200        asm volatile (
    … …  
    205207/** Returns level 0 page table entry flags.
    206208 *
    207  *  @param pt     Level 0 page table.
    208  *  @param i      Index of the entry to return.
    209  */
    210 static inline int get_pt_level0_flags(pte_t *pt, size_t i)
     209 * @param pt Level 0 page table.
     210 * @param i  Index of the entry to return.
     211 *
     212 */
     213NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
    211214{
    212215        pte_level0_t *p = &pt[i].l0;
    213216        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    214 
     217       
    215218        return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
    216219            (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
    … …  
    220223/** Returns level 1 page table entry flags.
    221224 *
    222  *  @param pt     Level 1 page table.
    223  *  @param i      Index of the entry to return.
    224  */
    225 static inline int get_pt_level1_flags(pte_t *pt, size_t i)
     225 * @param pt Level 1 page table.
     226 * @param i  Index of the entry to return.
     227 *
     228 */
     229NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
    226230{
    227231        pte_level1_t *p = &pt[i].l1;
    228 
     232       
    229233        int dt = p->descriptor_type;
    230234        int ap = p->access_permission_0;
    231 
     235       
    232236        return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
    233237            ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
    … …  
    241245}
    242246
    243 
    244247/** Sets flags of level 0 page table entry.
    245248 *
    246  *  @param pt     level 0 page table
    247  *  @param i      index of the entry to be changed
    248  *  @param flags  new flags
    249  */
    250 static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
     249 * @param pt    level 0 page table
     250 * @param i     index of the entry to be changed
     251 * @param flags new flags
     252 *
     253 */
     254NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
    251255{
    252256        pte_level0_t *p = &pt[i].l0;
    253 
     257       
    254258        if (flags & PAGE_NOT_PRESENT) {
    255259                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    … …  
    262266                p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
    263267                p->should_be_zero = 0;
    264     }
     268        }
    265269}
    266270
    … …  
    268272/** Sets flags of level 1 page table entry.
    269273 *
    270  *  We use same access rights for the whole page. When page is not preset we
    271  *  store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
    272  *  page entry, see #PAGE_VALID_ARCH).
    273  *
    274  *  @param pt     Level 1 page table.
    275  *  @param i      Index of the entry to be changed.
    276  *  @param flags  New flags.
    277  */ 
    278 static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
     274 * We use same access rights for the whole page. When page
     275 * is not preset we store 1 in acess_rigts_3 so that at least
     276 * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
     277 *
     278 * @param pt    Level 1 page table.
     279 * @param i     Index of the entry to be changed.
     280 * @param flags New flags.
     281 *
     282 */
     283NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
    279284{
    280285        pte_level1_t *p = &pt[i].l1;
    … …  
    287292                p->access_permission_3 = p->access_permission_0;
    288293        }
    289  
     294       
    290295        p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
    291 
     296       
    292297        /* default access permission */
    293298        p->access_permission_0 = p->access_permission_1 =
    294299            p->access_permission_2 = p->access_permission_3 =
    295300            PTE_AP_USER_NO_KERNEL_RW;
    296 
     301       
    297302        if (flags & PAGE_USER)  {
    298303                if (flags & PAGE_READ) {

  • kernel/arch/arm32/include/mm/tlb.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */

  • kernel/arch/ia32/include/asm.h

    re3ee9b9 r7a0359b  
    4141#include <typedefs.h>
    4242#include <config.h>
     43#include <trace.h>
    4344
    4445extern uint32_t interrupt_handler_size;
    4546
    46 extern void paging_on(void);
    47 
    48 extern void interrupt_handlers(void);
    49 
    50 extern void enable_l_apic_in_msr(void);
    51 
    52 
    53 extern void asm_delay_loop(uint32_t t);
    54 extern void asm_fake_loop(uint32_t t);
    55 
    56 
    5747/** Halt CPU
    5848 *
    … …  
    6050 *
    6151 */
    62 static inline __attribute__((noreturn)) void cpu_halt(void)
     52NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
    6353{
    6454        while (true) {
    … …  
    6959}
    7060
    71 static inline void cpu_sleep(void)
    72 {
    73         asm volatile ("hlt\n");
    74 }
    75 
    76 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     61NO_TRACE static inline void cpu_sleep(void)
     62{
     63        asm volatile (
     64                "hlt\n"
     65        );
     66}
     67
     68#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
    7769        { \
    7870                unative_t res; \
    … …  
    8476        }
    8577
    86 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     78#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
    8779        { \
    8880                asm volatile ( \
    … …  
    119111 *
    120112 */
    121 static inline void pio_write_8(ioport8_t *port, uint8_t val)
     113NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
    122114{
    123115        asm volatile (
    124116                "outb %b[val], %w[port]\n"
    125                 :: [val] "a" (val), [port] "d" (port)
     117                :: [val] "a" (val),
     118                   [port] "d" (port)
    126119        );
    127120}
    … …  
    135128 *
    136129 */
    137 static inline void pio_write_16(ioport16_t *port, uint16_t val)
     130NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
    138131{
    139132        asm volatile (
    140133                "outw %w[val], %w[port]\n"
    141                 :: [val] "a" (val), [port] "d" (port)
     134                :: [val] "a" (val),
     135                   [port] "d" (port)
    142136        );
    143137}
    … …  
    151145 *
    152146 */
    153 static inline void pio_write_32(ioport32_t *port, uint32_t val)
     147NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
    154148{
    155149        asm volatile (
    156150                "outl %[val], %w[port]\n"
    157                 :: [val] "a" (val), [port] "d" (port)
     151                :: [val] "a" (val),
     152                   [port] "d" (port)
    158153        );
    159154}
    … …  
    167162 *
    168163 */
    169 static inline uint8_t pio_read_8(ioport8_t *port)
     164NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    170165{
    171166        uint8_t val;
    … …  
    188183 *
    189184 */
    190 static inline uint16_t pio_read_16(ioport16_t *port)
     185NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    191186{
    192187        uint16_t val;
    … …  
    209204 *
    210205 */
    211 static inline uint32_t pio_read_32(ioport32_t *port)
     206NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    212207{
    213208        uint32_t val;
    … …  
    230225 *
    231226 */
    232 static inline ipl_t interrupts_enable(void)
     227NO_TRACE static inline ipl_t interrupts_enable(void)
    233228{
    234229        ipl_t v;
    … …  
    252247 *
    253248 */
    254 static inline ipl_t interrupts_disable(void)
     249NO_TRACE static inline ipl_t interrupts_disable(void)
    255250{
    256251        ipl_t v;
    … …  
    273268 *
    274269 */
    275 static inline void interrupts_restore(ipl_t ipl)
     270NO_TRACE static inline void interrupts_restore(ipl_t ipl)
    276271{
    277272        asm volatile (
    … …  
    287282 *
    288283 */
    289 static inline ipl_t interrupts_read(void)
     284NO_TRACE static inline ipl_t interrupts_read(void)
    290285{
    291286        ipl_t v;
    … …  
    305300 *
    306301 */
    307 static inline bool interrupts_disabled(void)
     302NO_TRACE static inline bool interrupts_disabled(void)
    308303{
    309304        ipl_t v;
    … …  
    319314
    320315/** Write to MSR */
    321 static inline void write_msr(uint32_t msr, uint64_t value)
     316NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
    322317{
    323318        asm volatile (
    324319                "wrmsr"
    325                 :: "c" (msr), "a" ((uint32_t) (value)),
     320                :: "c" (msr),
     321                   "a" ((uint32_t) (value)),
    326322                   "d" ((uint32_t) (value >> 32))
    327323        );
    328324}
    329325
    330 static inline uint64_t read_msr(uint32_t msr)
     326NO_TRACE static inline uint64_t read_msr(uint32_t msr)
    331327{
    332328        uint32_t ax, dx;
    … …  
    334330        asm volatile (
    335331                "rdmsr"
    336                 : "=a" (ax), "=d" (dx)
     332                : "=a" (ax),
     333                  "=d" (dx)
    337334                : "c" (msr)
    338335        );
    … …  
    349346 *
    350347 */
    351 static inline uintptr_t get_stack_base(void)
     348NO_TRACE static inline uintptr_t get_stack_base(void)
    352349{
    353350        uintptr_t v;
    … …  
    367364 *
    368365 */
    369 static inline void invlpg(uintptr_t addr)
     366NO_TRACE static inline void invlpg(uintptr_t addr)
    370367{
    371368        asm volatile (
    … …  
    380377 *
    381378 */
    382 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
     379NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
    383380{
    384381        asm volatile (
    … …  
    393390 *
    394391 */
    395 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
     392NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
    396393{
    397394        asm volatile (
    … …  
    406403 *
    407404 */
    408 static inline void idtr_load(ptr_16_32_t *idtr_reg)
     405NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
    409406{
    410407        asm volatile (
    … …  
    419416 *
    420417 */
    421 static inline void tr_load(uint16_t sel)
     418NO_TRACE static inline void tr_load(uint16_t sel)
    422419{
    423420        asm volatile (
    … …  
    427424}
    428425
     426extern void paging_on(void);
     427extern void interrupt_handlers(void);
     428extern void enable_l_apic_in_msr(void);
     429
     430extern void asm_delay_loop(uint32_t);
     431extern void asm_fake_loop(uint32_t);
     432
    429433#endif
    430434

  • kernel/arch/ia32/include/atomic.h

    re3ee9b9 r7a0359b  
    3939#include <arch/barrier.h>
    4040#include <preemption.h>
     41#include <trace.h>
    4142
    42 static inline void atomic_inc(atomic_t *val)
     43NO_TRACE static inline void atomic_inc(atomic_t *val)
    4344{
    4445#ifdef CONFIG_SMP
    … …  
    5556}
    5657
    57 static inline void atomic_dec(atomic_t *val)
     58NO_TRACE static inline void atomic_dec(atomic_t *val)
    5859{
    5960#ifdef CONFIG_SMP
    … …  
    7071}
    7172
    72 static inline atomic_count_t atomic_postinc(atomic_t *val)
     73NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    7374{
    7475        atomic_count_t r = 1;
    … …  
    8384}
    8485
    85 static inline atomic_count_t atomic_postdec(atomic_t *val)
     86NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    8687{
    8788        atomic_count_t r = -1;
    … …  
    99100#define atomic_predec(val)  (atomic_postdec(val) - 1)
    100101
    101 static inline atomic_count_t test_and_set(atomic_t *val)
     102NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
    102103{
    103104        atomic_count_t v = 1;
    … …  
    113114
    114115/** ia32 specific fast spinlock */
    115 static inline void atomic_lock_arch(atomic_t *val)
     116NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    116117{
    117118        atomic_count_t tmp;

  • kernel/arch/ia32/include/barrier.h

    re3ee9b9 r7a0359b  
    3636#define KERN_ia32_BARRIER_H_
    3737
     38#include <trace.h>
     39
    3840/*
    3941 * NOTE:
    … …  
    5052#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
    5153
    52 static inline void cpuid_serialization(void)
     54NO_TRACE static inline void cpuid_serialization(void)
    5355{
    5456        asm volatile (

  • kernel/arch/ia32/include/cycle.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_CYCLE_H_
    3737
    38 static inline uint64_t get_cycle(void)
     38#include <trace.h>
     39
     40NO_TRACE static inline uint64_t get_cycle(void)
    3941{
    4042        uint64_t v;

  • kernel/arch/ia32/include/interrupt.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <arch/pm.h>
     40#include <trace.h>
    4041
    41 #define IVT_ITEMS       IDT_ITEMS
    42 #define IVT_FIRST       0
     42#define IVT_ITEMS  IDT_ITEMS
     43#define IVT_FIRST  0
    4344
    44 #define EXC_COUNT       32
    45 #define IRQ_COUNT       16
     45#define EXC_COUNT  32
     46#define IRQ_COUNT  16
    4647
    47 #define IVT_EXCBASE     0
    48 #define IVT_IRQBASE     (IVT_EXCBASE + EXC_COUNT)
    49 #define IVT_FREEBASE    (IVT_IRQBASE + IRQ_COUNT)
     48#define IVT_EXCBASE   0
     49#define IVT_IRQBASE   (IVT_EXCBASE + EXC_COUNT)
     50#define IVT_FREEBASE  (IVT_IRQBASE + IRQ_COUNT)
    5051
    51 #define IRQ_CLK         0
    52 #define IRQ_KBD         1
    53 #define IRQ_PIC1        2
    54 #define IRQ_PIC_SPUR    7
    55 #define IRQ_MOUSE       12
    56 #define IRQ_DP8390      9
     52#define IRQ_CLK       0
     53#define IRQ_KBD       1
     54#define IRQ_PIC1      2
     55#define IRQ_PIC_SPUR  7
     56#define IRQ_MOUSE     12
     57#define IRQ_DP8390    9
    5758
    58 /* this one must have four least significant bits set to ones */
    59 #define VECTOR_APIC_SPUR        (IVT_ITEMS - 1)
     59/* This one must have four least significant bits set to ones */
     60#define VECTOR_APIC_SPUR  (IVT_ITEMS - 1)
    6061
    6162#if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
    … …  
    6364#endif
    6465
    65 #define VECTOR_DEBUG                    1
    66 #define VECTOR_CLK                      (IVT_IRQBASE + IRQ_CLK)
    67 #define VECTOR_PIC_SPUR                 (IVT_IRQBASE + IRQ_PIC_SPUR)
    68 #define VECTOR_SYSCALL                  IVT_FREEBASE
    69 #define VECTOR_TLB_SHOOTDOWN_IPI        (IVT_FREEBASE + 1)
    70 #define VECTOR_DEBUG_IPI                (IVT_FREEBASE + 2)
     66#define VECTOR_DEBUG              1
     67#define VECTOR_CLK                (IVT_IRQBASE + IRQ_CLK)
     68#define VECTOR_PIC_SPUR           (IVT_IRQBASE + IRQ_PIC_SPUR)
     69#define VECTOR_SYSCALL            IVT_FREEBASE
     70#define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
     71#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
    7172
    7273typedef struct istate {
    … …  
    7980        uint32_t ebp;
    8081       
    81         uint32_t ebp_frame;     /* imitation of frame pointer linkage */
    82         uint32_t eip_frame;     /* imitation of return address linkage */
    83 
     82        uint32_t ebp_frame;  /* imitation of frame pointer linkage */
     83        uint32_t eip_frame;  /* imitation of return address linkage */
     84       
    8485        uint32_t gs;
    8586        uint32_t fs;
    8687        uint32_t es;
    8788        uint32_t ds;
    88 
    89         uint32_t error_word;    /* real or fake error word */
     89       
     90        uint32_t error_word;  /* real or fake error word */
    9091        uint32_t eip;
    9192        uint32_t cs;
    9293        uint32_t eflags;
    93         uint32_t esp;           /* only if istate_t is from uspace */
    94         uint32_t ss;            /* only if istate_t is from uspace */
     94        uint32_t esp;         /* only if istate_t is from uspace */
     95        uint32_t ss;          /* only if istate_t is from uspace */
    9596} istate_t;
    9697
    9798/** Return true if exception happened while in userspace */
    98 static inline int istate_from_uspace(istate_t *istate)
     99NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    99100{
    100101        return !(istate->eip & 0x80000000);
    101102}
    102103
    103 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     104NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     105    uintptr_t retaddr)
    104106{
    105107        istate->eip = retaddr;
    106108}
    107109
    108 static inline unative_t istate_get_pc(istate_t *istate)
     110NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    109111{
    110112        return istate->eip;
    111113}
    112114
    113 static inline unative_t istate_get_fp(istate_t *istate)
     115NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    114116{
    115117        return istate->ebp;
    116118}
    117119
    118 extern void (* disable_irqs_function)(uint16_t irqmask);
    119 extern void (* enable_irqs_function)(uint16_t irqmask);
     120extern void (* disable_irqs_function)(uint16_t);
     121extern void (* enable_irqs_function)(uint16_t);
    120122extern void (* eoi_function)(void);
    121123
    122124extern void interrupt_init(void);
    123 extern void trap_virtual_enable_irqs(uint16_t irqmask);
    124 extern void trap_virtual_disable_irqs(uint16_t irqmask);
     125extern void trap_virtual_enable_irqs(uint16_t);
     126extern void trap_virtual_disable_irqs(uint16_t);
    125127
    126128#endif

  • kernel/arch/ia32/include/mm/page.h

    re3ee9b9 r7a0359b  
    3737
    3838#include <arch/mm/frame.h>
     39#include <trace.h>
    3940
    4041#define PAGE_WIDTH      FRAME_WIDTH
    … …  
    161162} __attribute__ ((packed)) pte_t;
    162163
    163 static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     164NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    164165{
    165166        pte_t *p = &pt[i];
    … …  
    174175}
    175176
    176 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     177NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    177178{
    178179        pte_t *p = &pt[i];

  • kernel/arch/ia64/include/asm.h

    re3ee9b9 r7a0359b  
    4040#include <typedefs.h>
    4141#include <arch/register.h>
     42#include <trace.h>
    4243
    4344#define IA64_IOSPACE_ADDRESS  0xE001000000000000ULL
    4445
    45 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     46NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    4647{
    4748        uintptr_t prt = (uintptr_t) port;
    … …  
    5657}
    5758
    58 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     59NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    5960{
    6061        uintptr_t prt = (uintptr_t) port;
    … …  
    6970}
    7071
    71 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     72NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    7273{
    7374        uintptr_t prt = (uintptr_t) port;
    … …  
    8283}
    8384
    84 static inline uint8_t pio_read_8(ioport8_t *port)
     85NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    8586{
    8687        uintptr_t prt = (uintptr_t) port;
    … …  
    9596}
    9697
    97 static inline uint16_t pio_read_16(ioport16_t *port)
     98NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    9899{
    99100        uintptr_t prt = (uintptr_t) port;
    … …  
    108109}
    109110
    110 static inline uint32_t pio_read_32(ioport32_t *port)
     111NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    111112{
    112113        uintptr_t prt = (uintptr_t) port;
    … …  
    126127 * The stack is assumed to be STACK_SIZE long.
    127128 * The stack must start on page boundary.
    128  */
    129 static inline uintptr_t get_stack_base(void)
    130 {
    131         uint64_t v;
    132        
    133         /* I'm not sure why but this code bad inlines in scheduler,
    134            so THE shifts about 16B and causes kernel panic
    135            
    136            asm volatile (
    137                "and %[value] = %[mask], r12"
    138                : [value] "=r" (v)
    139                : [mask] "r" (~(STACK_SIZE - 1))
    140            );
    141            return v;
    142            
    143            This code have the same meaning but inlines well.
    144         */
     129 *
     130 */
     131NO_TRACE static inline uintptr_t get_stack_base(void)
     132{
     133        uint64_t v;
     134       
     135        /*
     136         * I'm not sure why but this code inlines badly
     137         * in scheduler, resulting in THE shifting about
     138         * 16B and causing kernel panic.
     139         *
     140         * asm volatile (
     141         *     "and %[value] = %[mask], r12"
     142         *     : [value] "=r" (v)
     143         *     : [mask] "r" (~(STACK_SIZE - 1))
     144         * );
     145         * return v;
     146         *
     147         * The following code has the same semantics but
     148         * inlines correctly.
     149         *
     150         */
    145151       
    146152        asm volatile (
    … …  
    155161 *
    156162 * @return PSR.
    157  */
    158 static inline uint64_t psr_read(void)
     163 *
     164 */
     165NO_TRACE static inline uint64_t psr_read(void)
    159166{
    160167        uint64_t v;
    … …  
    171178 *
    172179 * @return Return location of interruption vector table.
    173  */
    174 static inline uint64_t iva_read(void)
     180 *
     181 */
     182NO_TRACE static inline uint64_t iva_read(void)
    175183{
    176184        uint64_t v;
    … …  
    187195 *
    188196 * @param v New location of interruption vector table.
    189  */
    190 static inline void iva_write(uint64_t v)
     197 *
     198 */
     199NO_TRACE static inline void iva_write(uint64_t v)
    191200{
    192201        asm volatile (
    … …  
    196205}
    197206
    198 
    199207/** Read IVR (External Interrupt Vector Register).
    200208 *
    201  * @return Highest priority, pending, unmasked external interrupt vector.
    202  */
    203 static inline uint64_t ivr_read(void)
     209 * @return Highest priority, pending, unmasked external
     210 *         interrupt vector.
     211 *
     212 */
     213NO_TRACE static inline uint64_t ivr_read(void)
    204214{
    205215        uint64_t v;
    … …  
    213223}
    214224
    215 static inline uint64_t cr64_read(void)
     225NO_TRACE static inline uint64_t cr64_read(void)
    216226{
    217227        uint64_t v;
    … …  
    225235}
    226236
    227 
    228237/** Write ITC (Interval Timer Counter) register.
    229238 *
    230239 * @param v New counter value.
    231  */
    232 static inline void itc_write(uint64_t v)
     240 *
     241 */
     242NO_TRACE static inline void itc_write(uint64_t v)
    233243{
    234244        asm volatile (
    … …  
    241251 *
    242252 * @return Current counter value.
    243  */
    244 static inline uint64_t itc_read(void)
     253 *
     254 */
     255NO_TRACE static inline uint64_t itc_read(void)
    245256{
    246257        uint64_t v;
    … …  
    257268 *
    258269 * @param v New match value.
    259  */
    260 static inline void itm_write(uint64_t v)
     270 *
     271 */
     272NO_TRACE static inline void itm_write(uint64_t v)
    261273{
    262274        asm volatile (
    … …  
    269281 *
    270282 * @return Match value.
    271  */
    272 static inline uint64_t itm_read(void)
     283 *
     284 */
     285NO_TRACE static inline uint64_t itm_read(void)
    273286{
    274287        uint64_t v;
    … …  
    285298 *
    286299 * @return Current vector and mask bit.
    287  */
    288 static inline uint64_t itv_read(void)
     300 *
     301 */
     302NO_TRACE static inline uint64_t itv_read(void)
    289303{
    290304        uint64_t v;
    … …  
    301315 *
    302316 * @param v New vector and mask bit.
    303  */
    304 static inline void itv_write(uint64_t v)
     317 *
     318 */
     319NO_TRACE static inline void itv_write(uint64_t v)
    305320{
    306321        asm volatile (
    … …  
    313328 *
    314329 * @param v This value is ignored.
    315  */
    316 static inline void eoi_write(uint64_t v)
     330 *
     331 */
     332NO_TRACE static inline void eoi_write(uint64_t v)
    317333{
    318334        asm volatile (
    … …  
    325341 *
    326342 * @return Current value of TPR.
    327  */
    328 static inline uint64_t tpr_read(void)
     343 *
     344 */
     345NO_TRACE static inline uint64_t tpr_read(void)
    329346{
    330347        uint64_t v;
    … …  
    341358 *
    342359 * @param v New value of TPR.
    343  */
    344 static inline void tpr_write(uint64_t v)
     360 *
     361 */
     362NO_TRACE static inline void tpr_write(uint64_t v)
    345363{
    346364        asm volatile (
    … …  
    356374 *
    357375 * @return Old interrupt priority level.
    358  */
    359 static ipl_t interrupts_disable(void)
     376 *
     377 */
     378NO_TRACE static ipl_t interrupts_disable(void)
    360379{
    361380        uint64_t v;
    … …  
    377396 *
    378397 * @return Old interrupt priority level.
    379  */
    380 static ipl_t interrupts_enable(void)
     398 *
     399 */
     400NO_TRACE static ipl_t interrupts_enable(void)
    381401{
    382402        uint64_t v;
    … …  
    399419 *
    400420 * @param ipl Saved interrupt priority level.
    401  */
    402 static inline void interrupts_restore(ipl_t ipl)
     421 *
     422 */
     423NO_TRACE static inline void interrupts_restore(ipl_t ipl)
    403424{
    404425        if (ipl & PSR_I_MASK)
    … …  
    411432 *
    412433 * @return PSR.
    413  */
    414 static inline ipl_t interrupts_read(void)
     434 *
     435 */
     436NO_TRACE static inline ipl_t interrupts_read(void)
    415437{
    416438        return (ipl_t) psr_read();
    … …  
    422444 *
    423445 */
    424 static inline bool interrupts_disabled(void)
     446NO_TRACE static inline bool interrupts_disabled(void)
    425447{
    426448        return !(psr_read() & PSR_I_MASK);
    … …  
    428450
    429451/** Disable protection key checking. */
    430 static inline void pk_disable(void)
     452NO_TRACE static inline void pk_disable(void)
    431453{
    432454        asm volatile (

  • kernel/arch/ia64/include/atomic.h

    re3ee9b9 r7a0359b  
    3636#define KERN_ia64_ATOMIC_H_
    3737
    38 static inline atomic_count_t test_and_set(atomic_t *val)
     38#include <trace.h>
     39
     40NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
    3941{
    4042        atomic_count_t v;
    … …  
    5052}
    5153
    52 static inline void atomic_lock_arch(atomic_t *val)
     54NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    5355{
    5456        do {
    … …  
    5759}
    5860
    59 static inline void atomic_inc(atomic_t *val)
     61NO_TRACE static inline void atomic_inc(atomic_t *val)
    6062{
    6163        atomic_count_t v;
    … …  
    6870}
    6971
    70 static inline void atomic_dec(atomic_t *val)
     72NO_TRACE static inline void atomic_dec(atomic_t *val)
    7173{
    7274        atomic_count_t v;
    … …  
    7981}
    8082
    81 static inline atomic_count_t atomic_preinc(atomic_t *val)
     83NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
    8284{
    8385        atomic_count_t v;
    … …  
    9294}
    9395
    94 static inline atomic_count_t atomic_predec(atomic_t *val)
     96NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
    9597{
    9698        atomic_count_t v;
    … …  
    105107}
    106108
    107 static inline atomic_count_t atomic_postinc(atomic_t *val)
     109NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    108110{
    109111        atomic_count_t v;
    … …  
    118120}
    119121
    120 static inline atomic_count_t atomic_postdec(atomic_t *val)
     122NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    121123{
    122124        atomic_count_t v;

  • kernel/arch/ia64/include/cpu.h

    re3ee9b9 r7a0359b  
    4040#include <arch/asm.h>
    4141#include <arch/bootinfo.h>
     42#include <trace.h>
    4243
    43 #define FAMILY_ITANIUM  0x7
    44 #define FAMILY_ITANIUM2 0x1f
     44#define FAMILY_ITANIUM   0x7
     45#define FAMILY_ITANIUM2  0x1f
     46
     47#define CR64_ID_SHIFT   24
     48#define CR64_ID_MASK    0xff000000
     49#define CR64_EID_SHIFT  16
     50#define CR64_EID_MASK   0xff0000
    4551
    4652typedef struct {
    … …  
    5561 *
    5662 * @return Value of CPUID[n] register.
     63 *
    5764 */
    58 static inline uint64_t cpuid_read(int n)
     65NO_TRACE static inline uint64_t cpuid_read(int n)
    5966{
    6067        uint64_t v;
    6168       
    62         asm volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n));
     69        asm volatile (
     70                "mov %[v] = cpuid[%[r]]\n"
     71                : [v] "=r" (v)
     72                : [r] "r" (n)
     73        );
    6374       
    6475        return v;
    6576}
    6677
    67 
    68 #define CR64_ID_SHIFT 24
    69 #define CR64_ID_MASK 0xff000000
    70 #define CR64_EID_SHIFT 16
    71 #define CR64_EID_MASK 0xff0000
    72 
    73 static inline int ia64_get_cpu_id(void)
     78NO_TRACE static inline int ia64_get_cpu_id(void)
    7479{
    75         uint64_t cr64=cr64_read();
    76         return ((CR64_ID_MASK)&cr64)>>CR64_ID_SHIFT;
     80        uint64_t cr64 = cr64_read();
     81        return ((CR64_ID_MASK) &cr64) >> CR64_ID_SHIFT;
    7782}
    7883
    79 static inline int ia64_get_cpu_eid(void)
     84NO_TRACE static inline int ia64_get_cpu_eid(void)
    8085{
    81         uint64_t cr64=cr64_read();
    82         return ((CR64_EID_MASK)&cr64)>>CR64_EID_SHIFT;
     86        uint64_t cr64 = cr64_read();
     87        return ((CR64_EID_MASK) &cr64) >> CR64_EID_SHIFT;
    8388}
    8489
    85 
    86 static inline void ipi_send_ipi(int id, int eid, int intno)
     90NO_TRACE static inline void ipi_send_ipi(int id, int eid, int intno)
    8791{
    8892        (bootinfo->sapic)[2 * (id * 256 + eid)] = intno;
    8993        srlz_d();
    90 
    9194}
    9295

  • kernel/arch/ia64/include/cycle.h

    re3ee9b9 r7a0359b  
    3636#define KERN_ia64_CYCLE_H_
    3737
    38 static inline uint64_t get_cycle(void)
     38#include <trace.h>
     39
     40NO_TRACE static inline uint64_t get_cycle(void)
    3941{
    4042        return 0;

  • kernel/arch/ia64/include/interrupt.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <arch/register.h>
     40#include <trace.h>
    4041
    4142/** ia64 has 256 INRs. */
    … …  
    133134} istate_t;
    134135
    135 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     136extern void *ivt;
     137
     138NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     139    uintptr_t retaddr)
    136140{
    137141        istate->cr_iip = retaddr;
    … …  
    139143}
    140144
    141 static inline unative_t istate_get_pc(istate_t *istate)
     145NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    142146{
    143147        return istate->cr_iip;
    144148}
    145149
    146 static inline unative_t istate_get_fp(istate_t *istate)
     150NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    147151{
    148         return 0;       /* FIXME */
     152        /* FIXME */
     153       
     154        return 0;
    149155}
    150156
    151 static inline int istate_from_uspace(istate_t *istate)
     157NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    152158{
    153159        return (istate->cr_iip) < 0xe000000000000000ULL;
    154160}
    155161
    156 extern void *ivt;
     162extern void general_exception(uint64_t, istate_t *);
     163extern int break_instruction(uint64_t, istate_t *);
     164extern void universal_handler(uint64_t, istate_t *);
     165extern void nop_handler(uint64_t, istate_t *);
     166extern void external_interrupt(uint64_t, istate_t *);
     167extern void disabled_fp_register(uint64_t, istate_t *);
    157168
    158 extern void general_exception(uint64_t vector, istate_t *istate);
    159 extern int break_instruction(uint64_t vector, istate_t *istate);
    160 extern void universal_handler(uint64_t vector, istate_t *istate);
    161 extern void nop_handler(uint64_t vector, istate_t *istate);
    162 extern void external_interrupt(uint64_t vector, istate_t *istate);
    163 extern void disabled_fp_register(uint64_t vector, istate_t *istate);
    164 
    165 extern void trap_virtual_enable_irqs(uint16_t irqmask);
     169extern void trap_virtual_enable_irqs(uint16_t);
    166170
    167171#endif

  • kernel/arch/ia64/include/mm/page.h

    re3ee9b9 r7a0359b  
    208208 * @return Address of the head of VHPT collision chain.
    209209 */
    210 static inline uint64_t thash(uint64_t va)
     210NO_TRACE static inline uint64_t thash(uint64_t va)
    211211{
    212212        uint64_t ret;
    … …  
    230230 * @return The unique tag for VPN and RID in the collision chain returned by thash().
    231231 */
    232 static inline uint64_t ttag(uint64_t va)
     232NO_TRACE static inline uint64_t ttag(uint64_t va)
    233233{
    234234        uint64_t ret;
    … …  
    249249 * @return Current contents of rr[i].
    250250 */
    251 static inline uint64_t rr_read(size_t i)
     251NO_TRACE static inline uint64_t rr_read(size_t i)
    252252{
    253253        uint64_t ret;
    … …  
    269269 * @param v Value to be written to rr[i].
    270270 */
    271 static inline void rr_write(size_t i, uint64_t v)
     271NO_TRACE static inline void rr_write(size_t i, uint64_t v)
    272272{
    273273        ASSERT(i < REGION_REGISTERS);
    … …  
    284284 * @return Current value stored in PTA.
    285285 */
    286 static inline uint64_t pta_read(void)
     286NO_TRACE static inline uint64_t pta_read(void)
    287287{
    288288        uint64_t ret;
    … …  
    300300 * @param v New value to be stored in PTA.
    301301 */
    302 static inline void pta_write(uint64_t v)
     302NO_TRACE static inline void pta_write(uint64_t v)
    303303{
    304304        asm volatile (

  • kernel/arch/mips32/include/asm.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <config.h>
     40#include <trace.h>
    4041
    41 static inline void cpu_sleep(void)
     42NO_TRACE static inline void cpu_sleep(void)
    4243{
    43         /* Most of the simulators do not support */
    44 /*      asm volatile ("wait"); */
     44        /*
     45         * Unfortunatelly most of the simulators do not support
     46         *
     47         * asm volatile (
     48         *     "wait"
     49         * );
     50         *
     51         */
    4552}
    4653
    … …  
    5259 *
    5360 */
    54 static inline uintptr_t get_stack_base(void)
     61NO_TRACE static inline uintptr_t get_stack_base(void)
    5562{
    5663        uintptr_t base;
    … …  
    6572}
    6673
    67 extern void cpu_halt(void) __attribute__((noreturn));
    68 extern void asm_delay_loop(uint32_t t);
    69 extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg,
    70     uintptr_t entry);
    71 
    72 extern ipl_t interrupts_disable(void);
    73 extern ipl_t interrupts_enable(void);
    74 extern void interrupts_restore(ipl_t ipl);
    75 extern ipl_t interrupts_read(void);
    76 extern bool interrupts_disabled(void);
    77 
    78 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     74NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    7975{
    8076        *port = v;
    8177}
    8278
    83 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     79NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    8480{
    8581        *port = v;
    8682}
    8783
    88 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     84NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    8985{
    9086        *port = v;
    9187}
    9288
    93 static inline uint8_t pio_read_8(ioport8_t *port)
     89NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    9490{
    9591        return *port;
    9692}
    9793
    98 static inline uint16_t pio_read_16(ioport16_t *port)
     94NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    9995{
    10096        return *port;
    10197}
    10298
    103 static inline uint32_t pio_read_32(ioport32_t *port)
     99NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    104100{
    105101        return *port;
    106102}
     103
     104extern void cpu_halt(void) __attribute__((noreturn));
     105extern void asm_delay_loop(uint32_t);
     106extern void userspace_asm(uintptr_t, uintptr_t, uintptr_t);
     107
     108extern ipl_t interrupts_disable(void);
     109extern ipl_t interrupts_enable(void);
     110extern void interrupts_restore(ipl_t);
     111extern ipl_t interrupts_read(void);
     112extern bool interrupts_disabled(void);
    107113
    108114#endif

  • kernel/arch/mips32/include/atomic.h

    re3ee9b9 r7a0359b  
    3636#define KERN_mips32_ATOMIC_H_
    3737
     38#include <trace.h>
     39
    3840#define atomic_inc(x)  ((void) atomic_add(x, 1))
    3941#define atomic_dec(x)  ((void) atomic_add(x, -1))
    … …  
    5355 *
    5456 */
    55 static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
     57NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
     58    atomic_count_t i)
    5659{
    5760        atomic_count_t tmp;
    … …  
    7679}
    7780
    78 static inline atomic_count_t test_and_set(atomic_t *val)
     81NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
    7982{
    8083        atomic_count_t tmp;
    … …  
    98101}
    99102
    100 static inline void atomic_lock_arch(atomic_t *val)
     103NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    101104{
    102105        do {

  • kernel/arch/mips32/include/barrier.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3939 * TODO: implement true MIPS memory barriers for macros below.
    4040 */
    41 #define CS_ENTER_BARRIER()      asm volatile ("" ::: "memory")
    42 #define CS_LEAVE_BARRIER()      asm volatile ("" ::: "memory")
     41#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
     42#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
    4343
    44 #define memory_barrier()        asm volatile ("" ::: "memory")
    45 #define read_barrier()          asm volatile ("" ::: "memory")
    46 #define write_barrier()         asm volatile ("" ::: "memory")
     44#define memory_barrier() asm volatile ("" ::: "memory")
     45#define read_barrier()   asm volatile ("" ::: "memory")
     46#define write_barrier()  asm volatile ("" ::: "memory")
    4747
    4848#define smc_coherence(a)

  • kernel/arch/mips32/include/cycle.h

    re3ee9b9 r7a0359b  
    3838#include <arch/cp0.h>
    3939#include <arch/interrupt.h>
     40#include <trace.h>
    4041
    41 static inline uint64_t get_cycle(void)
     42NO_TRACE static inline uint64_t get_cycle(void)
    4243{
    4344        return ((uint64_t) count_hi << 32) + ((uint64_t) cp0_count_read());

  • kernel/arch/mips32/include/exception.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3838#include <typedefs.h>
    3939#include <arch/cp0.h>
     40#include <trace.h>
    4041
    41 #define EXC_Int         0
    42 #define EXC_Mod         1
    43 #define EXC_TLBL        2
    44 #define EXC_TLBS        3
    45 #define EXC_AdEL        4
    46 #define EXC_AdES        5
    47 #define EXC_IBE         6
    48 #define EXC_DBE         7
    49 #define EXC_Sys         8
    50 #define EXC_Bp          9
    51 #define EXC_RI          10
    52 #define EXC_CpU         11
    53 #define EXC_Ov          12
    54 #define EXC_Tr          13
    55 #define EXC_VCEI        14
    56 #define EXC_FPE         15
    57 #define EXC_WATCH       23
    58 #define EXC_VCED        31
     42#define EXC_Int    0
     43#define EXC_Mod    1
     44#define EXC_TLBL   2
     45#define EXC_TLBS   3
     46#define EXC_AdEL   4
     47#define EXC_AdES   5
     48#define EXC_IBE    6
     49#define EXC_DBE    7
     50#define EXC_Sys    8
     51#define EXC_Bp     9
     52#define EXC_RI     10
     53#define EXC_CpU    11
     54#define EXC_Ov     12
     55#define EXC_Tr     13
     56#define EXC_VCEI   14
     57#define EXC_FPE    15
     58#define EXC_WATCH  23
     59#define EXC_VCED   31
    5960
    6061typedef struct istate {
    … …  
    8283        uint32_t lo;
    8384        uint32_t hi;
    84 
    85         uint32_t status; /* cp0_status */
    86         uint32_t epc; /* cp0_epc */
    87         uint32_t k1; /* We use it as thread-local pointer */
     85       
     86        uint32_t status;  /* cp0_status */
     87        uint32_t epc;     /* cp0_epc */
     88        uint32_t k1;      /* We use it as thread-local pointer */
    8889} istate_t;
    8990
    90 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     91NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     92    uintptr_t retaddr)
    9193{
    9294        istate->epc = retaddr;
    … …  
    9496
    9597/** Return true if exception happened while in userspace */
    96 static inline int istate_from_uspace(istate_t *istate)
     98NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    9799{
    98100        return istate->status & cp0_status_um_bit;
    99101}
    100 static inline unative_t istate_get_pc(istate_t *istate)
     102
     103NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    101104{
    102105        return istate->epc;
    103106}
    104 static inline unative_t istate_get_fp(istate_t *istate)
     107
     108NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    105109{
    106         return 0;       /* FIXME */
     110        /* FIXME */
     111       
     112        return 0;
    107113}
    108114

  • kernel/arch/mips32/include/faddr.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3838#include <typedefs.h>
    3939
    40 #define FADDR(fptr)             ((uintptr_t) (fptr))
     40#define FADDR(fptr)  ((uintptr_t) (fptr))
    4141
    4242#endif

  • kernel/arch/mips32/include/mm/page.h

    re3ee9b9 r7a0359b  
    3737
    3838#include <arch/mm/frame.h>
     39#include <trace.h>
    3940
    4041#define PAGE_WIDTH      FRAME_WIDTH
    … …  
    155156
    156157
    157 static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     158NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    158159{
    159160        pte_t *p = &pt[i];
    … …  
    168169}
    169170
    170 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     171NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    171172{
    172173        pte_t *p = &pt[i];

  • kernel/arch/mips32/include/mm/tlb.h

    re3ee9b9 r7a0359b  
    3939#include <arch/mm/asid.h>
    4040#include <arch/exception.h>
     41#include <trace.h>
    4142
    4243#define TLB_ENTRY_COUNT  48
    … …  
    126127 * Probe TLB for Matching Entry.
    127128 */
    128 static inline void tlbp(void)
     129NO_TRACE static inline void tlbp(void)
    129130{
    130131        asm volatile ("tlbp\n\t");
    … …  
    136137 * Read Indexed TLB Entry.
    137138 */
    138 static inline void tlbr(void)
     139NO_TRACE static inline void tlbr(void)
    139140{
    140141        asm volatile ("tlbr\n\t");
    … …  
    145146 * Write Indexed TLB Entry.
    146147 */
    147 static inline void tlbwi(void)
     148NO_TRACE static inline void tlbwi(void)
    148149{
    149150        asm volatile ("tlbwi\n\t");
    … …  
    154155 * Write Random TLB Entry.
    155156 */
    156 static inline void tlbwr(void)
     157NO_TRACE static inline void tlbwr(void)
    157158{
    158159        asm volatile ("tlbwr\n\t");

  • kernel/arch/ppc32/include/asm.h

    re3ee9b9 r7a0359b  
    4040#include <arch/cpu.h>
    4141#include <arch/mm/asid.h>
    42 
    43 static inline uint32_t msr_read(void)
     42#include <trace.h>
     43
     44NO_TRACE static inline uint32_t msr_read(void)
    4445{
    4546        uint32_t msr;
    … …  
    5354}
    5455
    55 static inline void msr_write(uint32_t msr)
     56NO_TRACE static inline void msr_write(uint32_t msr)
    5657{
    5758        asm volatile (
    … …  
    6162}
    6263
    63 static inline void sr_set(uint32_t flags, asid_t asid, uint32_t sr)
     64NO_TRACE static inline void sr_set(uint32_t flags, asid_t asid, uint32_t sr)
    6465{
    6566        asm volatile (
    … …  
    7071}
    7172
    72 static inline uint32_t sr_get(uint32_t vaddr)
     73NO_TRACE static inline uint32_t sr_get(uint32_t vaddr)
    7374{
    7475        uint32_t vsid;
    … …  
    8384}
    8485
    85 static inline uint32_t sdr1_get(void)
     86NO_TRACE static inline uint32_t sdr1_get(void)
    8687{
    8788        uint32_t sdr1;
    … …  
    103104 *
    104105 */
    105 static inline ipl_t interrupts_enable(void)
     106NO_TRACE static inline ipl_t interrupts_enable(void)
    106107{
    107108        ipl_t ipl = msr_read();
    … …  
    118119 *
    119120 */
    120 static inline ipl_t interrupts_disable(void)
     121NO_TRACE static inline ipl_t interrupts_disable(void)
    121122{
    122123        ipl_t ipl = msr_read();
    … …  
    132133 *
    133134 */
    134 static inline void interrupts_restore(ipl_t ipl)
     135NO_TRACE static inline void interrupts_restore(ipl_t ipl)
    135136{
    136137        msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE));
    … …  
    144145 *
    145146 */
    146 static inline ipl_t interrupts_read(void)
     147NO_TRACE static inline ipl_t interrupts_read(void)
    147148{
    148149        return msr_read();
    … …  
    154155 *
    155156 */
    156 static inline bool interrupts_disabled(void)
     157NO_TRACE static inline bool interrupts_disabled(void)
    157158{
    158159        return ((msr_read() & MSR_EE) == 0);
    … …  
    166167 *
    167168 */
    168 static inline uintptr_t get_stack_base(void)
     169NO_TRACE static inline uintptr_t get_stack_base(void)
    169170{
    170171        uintptr_t base;
    … …  
    179180}
    180181
    181 static inline void cpu_sleep(void)
    182 {
     182NO_TRACE static inline void cpu_sleep(void)
     183{
     184}
     185
     186NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
     187{
     188        *port = v;
     189}
     190
     191NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
     192{
     193        *port = v;
     194}
     195
     196NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
     197{
     198        *port = v;
     199}
     200
     201NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
     202{
     203        return *port;
     204}
     205
     206NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
     207{
     208        return *port;
     209}
     210
     211NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
     212{
     213        return *port;
    183214}
    184215
    … …  
    187218extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry);
    188219
    189 static inline void pio_write_8(ioport8_t *port, uint8_t v)
    190 {
    191         *port = v;
    192 }
    193 
    194 static inline void pio_write_16(ioport16_t *port, uint16_t v)
    195 {
    196         *port = v;
    197 }
    198 
    199 static inline void pio_write_32(ioport32_t *port, uint32_t v)
    200 {
    201         *port = v;
    202 }
    203 
    204 static inline uint8_t pio_read_8(ioport8_t *port)
    205 {
    206         return *port;
    207 }
    208 
    209 static inline uint16_t pio_read_16(ioport16_t *port)
    210 {
    211         return *port;
    212 }
    213 
    214 static inline uint32_t pio_read_32(ioport32_t *port)
    215 {
    216         return *port;
    217 }
    218 
    219220#endif
    220221

  • kernel/arch/ppc32/include/atomic.h

    re3ee9b9 r7a0359b  
    3636#define KERN_ppc32_ATOMIC_H_
    3737
    38 static inline void atomic_inc(atomic_t *val)
     38#include <trace.h>
     39
     40NO_TRACE static inline void atomic_inc(atomic_t *val)
    3941{
    4042        atomic_count_t tmp;
    … …  
    5456}
    5557
    56 static inline void atomic_dec(atomic_t *val)
     58NO_TRACE static inline void atomic_dec(atomic_t *val)
    5759{
    5860        atomic_count_t tmp;
    … …  
    7274}
    7375
    74 static inline atomic_count_t atomic_postinc(atomic_t *val)
     76NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    7577{
    7678        atomic_inc(val);
    … …  
    7880}
    7981
    80 static inline atomic_count_t atomic_postdec(atomic_t *val)
     82NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    8183{
    8284        atomic_dec(val);
    … …  
    8486}
    8587
    86 static inline atomic_count_t atomic_preinc(atomic_t *val)
     88NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
    8789{
    8890        atomic_inc(val);
    … …  
    9092}
    9193
    92 static inline atomic_count_t atomic_predec(atomic_t *val)
     94NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
    9395{
    9496        atomic_dec(val);

  • kernel/arch/ppc32/include/barrier.h

    re3ee9b9 r7a0359b  
    3636#define KERN_ppc32_BARRIER_H_
    3737
     38#include <trace.h>
     39
    3840#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
    3941#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
    … …  
    5860 */
    5961
    60 static inline void smc_coherence(void *addr)
     62NO_TRACE static inline void smc_coherence(void *addr)
    6163{
    6264        asm volatile (
    … …  
    7072}
    7173
    72 static inline void smc_coherence_block(void *addr, unsigned int len)
     74NO_TRACE static inline void smc_coherence_block(void *addr, unsigned int len)
    7375{
    7476        unsigned int i;

  • kernel/arch/ppc32/include/cpu.h

    re3ee9b9 r7a0359b  
    5252
    5353#include <typedefs.h>
     54#include <trace.h>
    5455
    5556typedef struct {
    … …  
    5859} __attribute__ ((packed)) cpu_arch_t;
    5960
    60 static inline void cpu_version(cpu_arch_t *info)
     61NO_TRACE static inline void cpu_version(cpu_arch_t *info)
    6162{
    6263        asm volatile (

  • kernel/arch/ppc32/include/cycle.h

    re3ee9b9 r7a0359b  
    3636#define KERN_ppc32_CYCLE_H_
    3737
    38 static inline uint64_t get_cycle(void)
     38#include <trace.h>
     39
     40NO_TRACE static inline uint64_t get_cycle(void)
    3941{
    4042        uint32_t lower;

  • kernel/arch/ppc32/include/exception.h

    re3ee9b9 r7a0359b  
    3838#include <typedefs.h>
    3939#include <arch/cpu.h>
     40#include <trace.h>
    4041
    4142typedef struct istate {
    … …  
    8182} istate_t;
    8283
    83 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     84NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     85    uintptr_t retaddr)
    8486{
    8587        istate->pc = retaddr;
    … …  
    9193 *
    9294 */
    93 static inline int istate_from_uspace(istate_t *istate)
     95NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    9496{
    9597        return (istate->srr1 & MSR_PR) != 0;
    9698}
    9799
    98 static inline unative_t istate_get_pc(istate_t *istate)
     100NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    99101{
    100102        return istate->pc;
    101103}
    102104
    103 static inline unative_t istate_get_fp(istate_t *istate)
     105NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    104106{
    105107        return istate->sp;

  • kernel/arch/ppc32/include/mm/frame.h

    re3ee9b9 r7a0359b  
    4343
    4444#include <typedefs.h>
     45#include <trace.h>
    4546
    4647extern uintptr_t last_frame;
    4748
    48 static inline uint32_t physmem_top(void)
     49NO_TRACE static inline uint32_t physmem_top(void)
    4950{
    5051        uint32_t physmem;

  • kernel/arch/ppc32/include/mm/page.h

    re3ee9b9 r7a0359b  
    3737
    3838#include <arch/mm/frame.h>
     39#include <trace.h>
    3940
    4041#define PAGE_WIDTH  FRAME_WIDTH
    … …  
    153154} pte_t;
    154155
    155 static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     156NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    156157{
    157158        pte_t *entry = &pt[i];
    … …  
    166167}
    167168
    168 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     169NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    169170{
    170171        pte_t *entry = &pt[i];

  • kernel/arch/sparc64/include/asm.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    4343#include <arch/stack.h>
    4444#include <arch/barrier.h>
    45 
    46 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     45#include <trace.h>
     46
     47NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    4748{
    4849        *port = v;
    … …  
    5051}
    5152
    52 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     53NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    5354{
    5455        *port = v;
    … …  
    5657}
    5758
    58 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     59NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    5960{
    6061        *port = v;
    … …  
    6263}
    6364
    64 static inline uint8_t pio_read_8(ioport8_t *port)
    65 {
    66         uint8_t rv;
    67 
    68         rv = *port;
     65NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
     66{
     67        uint8_t rv = *port;
    6968        memory_barrier();
    70 
    7169        return rv;
    7270}
    7371
    74 static inline uint16_t pio_read_16(ioport16_t *port)
    75 {
    76         uint16_t rv;
    77 
    78         rv = *port;
     72NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
     73{
     74        uint16_t rv = *port;
    7975        memory_barrier();
    80 
    8176        return rv;
    8277}
    8378
    84 static inline uint32_t pio_read_32(ioport32_t *port)
    85 {
    86         uint32_t rv;
    87 
    88         rv = *port;
     79NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
     80{
     81        uint32_t rv = *port;
    8982        memory_barrier();
    90 
    9183        return rv;
    9284}
    … …  
    9587 *
    9688 * @return Value of PSTATE register.
    97  */
    98 static inline uint64_t pstate_read(void)
    99 {
    100         uint64_t v;
    101        
    102         asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
     89 *
     90 */
     91NO_TRACE static inline uint64_t pstate_read(void)
     92{
     93        uint64_t v;
     94       
     95        asm volatile (
     96                "rdpr %%pstate, %[v]\n"
     97                : [v] "=r" (v)
     98        );
    10399       
    104100        return v;
    … …  
    108104 *
    109105 * @param v New value of PSTATE register.
    110  */
    111 static inline void pstate_write(uint64_t v)
    112 {
    113         asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
     106 *
     107 */
     108NO_TRACE static inline void pstate_write(uint64_t v)
     109{
     110        asm volatile (
     111                "wrpr %[v], %[zero], %%pstate\n"
     112                :: [v] "r" (v),
     113                   [zero] "i" (0)
     114        );
    114115}
    115116
    … …  
    117118 *
    118119 * @return Value of TICK_comapre register.
    119  */
    120 static inline uint64_t tick_compare_read(void)
    121 {
    122         uint64_t v;
    123        
    124         asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
     120 *
     121 */
     122NO_TRACE static inline uint64_t tick_compare_read(void)
     123{
     124        uint64_t v;
     125       
     126        asm volatile (
     127                "rd %%tick_cmpr, %[v]\n"
     128                : [v] "=r" (v)
     129        );
    125130       
    126131        return v;
    … …  
    130135 *
    131136 * @param v New value of TICK_comapre register.
    132  */
    133 static inline void tick_compare_write(uint64_t v)
    134 {
    135         asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
     137 *
     138 */
     139NO_TRACE static inline void tick_compare_write(uint64_t v)
     140{
     141        asm volatile (
     142                "wr %[v], %[zero], %%tick_cmpr\n"
     143                :: [v] "r" (v),
     144                   [zero] "i" (0)
     145        );
    136146}
    137147
    … …  
    139149 *
    140150 * @return Value of STICK_compare register.
    141  */
    142 static inline uint64_t stick_compare_read(void)
    143 {
    144         uint64_t v;
    145        
    146         asm volatile ("rd %%asr25, %0\n" : "=r" (v));
     151 *
     152 */
     153NO_TRACE static inline uint64_t stick_compare_read(void)
     154{
     155        uint64_t v;
     156       
     157        asm volatile (
     158                "rd %%asr25, %[v]\n"
     159                : [v] "=r" (v)
     160        );
    147161       
    148162        return v;
    … …  
    152166 *
    153167 * @param v New value of STICK_comapre register.
    154  */
    155 static inline void stick_compare_write(uint64_t v)
    156 {
    157         asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
     168 *
     169 */
     170NO_TRACE static inline void stick_compare_write(uint64_t v)
     171{
     172        asm volatile (
     173                "wr %[v], %[zero], %%asr25\n"
     174                :: [v] "r" (v),
     175                   [zero] "i" (0)
     176        );
    158177}
    159178
    … …  
    161180 *
    162181 * @return Value of TICK register.
    163  */
    164 static inline uint64_t tick_read(void)
    165 {
    166         uint64_t v;
    167        
    168         asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
     182 *
     183 */
     184NO_TRACE static inline uint64_t tick_read(void)
     185{
     186        uint64_t v;
     187       
     188        asm volatile (
     189                "rdpr %%tick, %[v]\n"
     190                : [v] "=r" (v)
     191        );
    169192       
    170193        return v;
    … …  
    174197 *
    175198 * @param v New value of TICK register.
    176  */
    177 static inline void tick_write(uint64_t v)
    178 {
    179         asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
     199 *
     200 */
     201NO_TRACE static inline void tick_write(uint64_t v)
     202{
     203        asm volatile (
     204                "wrpr %[v], %[zero], %%tick\n"
     205                :: [v] "r" (v),
     206                   [zero] "i" (0)
     207        );
    180208}
    181209
    … …  
    183211 *
    184212 * @return Value of FPRS register.
    185  */
    186 static inline uint64_t fprs_read(void)
    187 {
    188         uint64_t v;
    189        
    190         asm volatile ("rd %%fprs, %0\n" : "=r" (v));
     213 *
     214 */
     215NO_TRACE static inline uint64_t fprs_read(void)
     216{
     217        uint64_t v;
     218       
     219        asm volatile (
     220                "rd %%fprs, %[v]\n"
     221                : [v] "=r" (v)
     222        );
    191223       
    192224        return v;
    … …  
    196228 *
    197229 * @param v New value of FPRS register.
    198  */
    199 static inline void fprs_write(uint64_t v)
    200 {
    201         asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
     230 *
     231 */
     232NO_TRACE static inline void fprs_write(uint64_t v)
     233{
     234        asm volatile (
     235                "wr %[v], %[zero], %%fprs\n"
     236                :: [v] "r" (v),
     237                   [zero] "i" (0)
     238        );
    202239}
    203240
    … …  
    205242 *
    206243 * @return Value of SOFTINT register.
    207  */
    208 static inline uint64_t softint_read(void)
    209 {
    210         uint64_t v;
    211 
    212         asm volatile ("rd %%softint, %0\n" : "=r" (v));
    213 
     244 *
     245 */
     246NO_TRACE static inline uint64_t softint_read(void)
     247{
     248        uint64_t v;
     249       
     250        asm volatile (
     251                "rd %%softint, %[v]\n"
     252                : [v] "=r" (v)
     253        );
     254       
    214255        return v;
    215256}
    … …  
    218259 *
    219260 * @param v New value of SOFTINT register.
    220  */
    221 static inline void softint_write(uint64_t v)
    222 {
    223         asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
     261 *
     262 */
     263NO_TRACE static inline void softint_write(uint64_t v)
     264{
     265        asm volatile (
     266                "wr %[v], %[zero], %%softint\n"
     267                :: [v] "r" (v),
     268                   [zero] "i" (0)
     269        );
    224270}
    225271
    … …  
    229275 *
    230276 * @param v New value of CLEAR_SOFTINT register.
    231  */
    232 static inline void clear_softint_write(uint64_t v)
    233 {
    234         asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
     277 *
     278 */
     279NO_TRACE static inline void clear_softint_write(uint64_t v)
     280{
     281        asm volatile (
     282                "wr %[v], %[zero], %%clear_softint\n"
     283                :: [v] "r" (v),
     284                   [zero] "i" (0)
     285        );
    235286}
    236287
    … …  
    240291 *
    241292 * @param v New value of SET_SOFTINT register.
    242  */
    243 static inline void set_softint_write(uint64_t v)
    244 {
    245         asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
     293 *
     294 */
     295NO_TRACE static inline void set_softint_write(uint64_t v)
     296{
     297        asm volatile (
     298                "wr %[v], %[zero], %%set_softint\n"
     299                :: [v] "r" (v),
     300                   [zero] "i" (0)
     301        );
    246302}
    247303
    … …  
    252308 *
    253309 * @return Old interrupt priority level.
    254  */
    255 static inline ipl_t interrupts_enable(void) {
     310 *
     311 */
     312NO_TRACE static inline ipl_t interrupts_enable(void) {
    256313        pstate_reg_t pstate;
    257         uint64_t value;
    258        
    259         value = pstate_read();
     314        uint64_t value = pstate_read();
     315       
    260316        pstate.value = value;
    261317        pstate.ie = true;
    … …  
    271327 *
    272328 * @return Old interrupt priority level.
    273  */
    274 static inline ipl_t interrupts_disable(void) {
     329 *
     330 */
     331NO_TRACE static inline ipl_t interrupts_disable(void) {
    275332        pstate_reg_t pstate;
    276         uint64_t value;
    277        
    278         value = pstate_read();
     333        uint64_t value = pstate_read();
     334       
    279335        pstate.value = value;
    280336        pstate.ie = false;
    … …  
    289345 *
    290346 * @param ipl Saved interrupt priority level.
    291  */
    292 static inline void interrupts_restore(ipl_t ipl) {
     347 *
     348 */
     349NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
    293350        pstate_reg_t pstate;
    294351       
    … …  
    303360 *
    304361 * @return Current interrupt priority level.
    305  */
    306 static inline ipl_t interrupts_read(void) {
     362 *
     363 */
     364NO_TRACE static inline ipl_t interrupts_read(void) {
    307365        return (ipl_t) pstate_read();
    308366}
    … …  
    313371 *
    314372 */
    315 static inline bool interrupts_disabled(void)
     373NO_TRACE static inline bool interrupts_disabled(void)
    316374{
    317375        pstate_reg_t pstate;
    318 
     376       
    319377        pstate.value = pstate_read();
    320378        return !pstate.ie;
    … …  
    326384 * The stack is assumed to be STACK_SIZE bytes long.
    327385 * The stack must start on page boundary.
    328  */
    329 static inline uintptr_t get_stack_base(void)
     386 *
     387 */
     388NO_TRACE static inline uintptr_t get_stack_base(void)
    330389{
    331390        uintptr_t unbiased_sp;
    332391       
    333         asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
     392        asm volatile (
     393                "add %%sp, %[stack_bias], %[unbiased_sp]\n"
     394                : [unbiased_sp] "=r" (unbiased_sp)
     395                : [stack_bias] "i" (STACK_BIAS)
     396        );
    334397       
    335398        return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
    … …  
    339402 *
    340403 * @return Value of VER register.
    341  */
    342 static inline uint64_t ver_read(void)
    343 {
    344         uint64_t v;
    345        
    346         asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
     404 *
     405 */
     406NO_TRACE static inline uint64_t ver_read(void)
     407{
     408        uint64_t v;
     409       
     410        asm volatile (
     411                "rdpr %%ver, %[v]\n"
     412                : [v] "=r" (v)
     413        );
    347414       
    348415        return v;
    … …  
    352419 *
    353420 * @return Current value in TPC.
    354  */
    355 static inline uint64_t tpc_read(void)
    356 {
    357         uint64_t v;
    358        
    359         asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
     421 *
     422 */
     423NO_TRACE static inline uint64_t tpc_read(void)
     424{
     425        uint64_t v;
     426       
     427        asm volatile (
     428                "rdpr %%tpc, %[v]\n"
     429                : [v] "=r" (v)
     430        );
    360431       
    361432        return v;
    … …  
    365436 *
    366437 * @return Current value in TL.
    367  */
    368 static inline uint64_t tl_read(void)
    369 {
    370         uint64_t v;
    371        
    372         asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
     438 *
     439 */
     440NO_TRACE static inline uint64_t tl_read(void)
     441{
     442        uint64_t v;
     443       
     444        asm volatile (
     445                "rdpr %%tl, %[v]\n"
     446                : [v] "=r" (v)
     447        );
    373448       
    374449        return v;
    … …  
    378453 *
    379454 * @return Current value in TBA.
    380  */
    381 static inline uint64_t tba_read(void)
    382 {
    383         uint64_t v;
    384        
    385         asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
     455 *
     456 */
     457NO_TRACE static inline uint64_t tba_read(void)
     458{
     459        uint64_t v;
     460       
     461        asm volatile (
     462                "rdpr %%tba, %[v]\n"
     463                : [v] "=r" (v)
     464        );
    386465       
    387466        return v;
    … …  
    391470 *
    392471 * @param v New value of TBA.
    393  */
    394 static inline void tba_write(uint64_t v)
    395 {
    396         asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
     472 *
     473 */
     474NO_TRACE static inline void tba_write(uint64_t v)
     475{
     476        asm volatile (
     477                "wrpr %[v], %[zero], %%tba\n"
     478                :: [v] "r" (v),
     479                   [zero] "i" (0)
     480        );
    397481}
    398482
    … …  
    400484 *
    401485 * @param asi ASI determining the alternate space.
    402  * @param va Virtual address within the ASI.
    403  *
    404  * @return Value read from the virtual address in the specified address space.
    405  */
    406 static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
    407 {
    408         uint64_t v;
    409        
    410         asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
     486 * @param va  Virtual address within the ASI.
     487 *
     488 * @return Value read from the virtual address in
     489 *         the specified address space.
     490 *
     491 */
     492NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
     493{
     494        uint64_t v;
     495       
     496        asm volatile (
     497                "ldxa [%[va]] %[asi], %[v]\n"
     498                : [v] "=r" (v)
     499                : [va] "r" (va),
     500                  [asi] "i" ((unsigned int) asi)
     501        );
    411502       
    412503        return v;
    … …  
    416507 *
    417508 * @param asi ASI determining the alternate space.
    418  * @param va Virtual address within the ASI.
    419  * @param v Value to be written.
    420  */
    421 static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
    422 {
    423         asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
     509 * @param va  Virtual address within the ASI.
     510 * @param v   Value to be written.
     511 *
     512 */
     513NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
     514{
     515        asm volatile (
     516                "stxa %[v], [%[va]] %[asi]\n"
     517                :: [v] "r" (v),
     518                   [va] "r" (va),
     519                   [asi] "i" ((unsigned int) asi)
     520                : "memory"
     521        );
    424522}
    425523
    426524/** Flush all valid register windows to memory. */
    427 static inline void flushw(void)
     525NO_TRACE static inline void flushw(void)
    428526{
    429527        asm volatile ("flushw\n");
    … …  
    431529
    432530/** Switch to nucleus by setting TL to 1. */
    433 static inline void nucleus_enter(void)
     531NO_TRACE static inline void nucleus_enter(void)
    434532{
    435533        asm volatile ("wrpr %g0, 1, %tl\n");
    … …  
    437535
    438536/** Switch from nucleus by setting TL to 0. */
    439 static inline void nucleus_leave(void)
     537NO_TRACE static inline void nucleus_leave(void)
    440538{
    441539        asm volatile ("wrpr %g0, %g0, %tl\n");

  • kernel/arch/sparc64/include/atomic.h

    re3ee9b9 r7a0359b  
    3939#include <typedefs.h>
    4040#include <preemption.h>
     41#include <trace.h>
    4142
    4243/** Atomic add operation.
    … …  
    5051 *
    5152 */
    52 static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
     53NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
     54    atomic_count_t i)
    5355{
    5456        atomic_count_t a;
    … …  
    7274}
    7375
    74 static inline atomic_count_t atomic_preinc(atomic_t *val)
     76NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
    7577{
    7678        return atomic_add(val, 1) + 1;
    7779}
    7880
    79 static inline atomic_count_t atomic_postinc(atomic_t *val)
     81NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    8082{
    8183        return atomic_add(val, 1);
    8284}
    8385
    84 static inline atomic_count_t atomic_predec(atomic_t *val)
     86NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
    8587{
    8688        return atomic_add(val, -1) - 1;
    8789}
    8890
    89 static inline atomic_count_t atomic_postdec(atomic_t *val)
     91NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    9092{
    9193        return atomic_add(val, -1);
    9294}
    9395
    94 static inline void atomic_inc(atomic_t *val)
     96NO_TRACE static inline void atomic_inc(atomic_t *val)
    9597{
    9698        (void) atomic_add(val, 1);
    9799}
    98100
    99 static inline void atomic_dec(atomic_t *val)
     101NO_TRACE static inline void atomic_dec(atomic_t *val)
    100102{
    101103        (void) atomic_add(val, -1);
    102104}
    103105
    104 static inline atomic_count_t test_and_set(atomic_t *val)
     106NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
    105107{
    106108        atomic_count_t v = 1;
    … …  
    117119}
    118120
    119 static inline void atomic_lock_arch(atomic_t *val)
     121NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    120122{
    121123        atomic_count_t tmp1 = 1;

  • kernel/arch/sparc64/include/barrier.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    3636#define KERN_sparc64_BARRIER_H_
    3737
     38#include <trace.h>
     39
    3840#ifdef KERNEL
     41
    3942#include <typedefs.h>
     43
    4044#else
     45
    4146#include <stdint.h>
     47
    4248#endif
    4349
    … …  
    4551 * Our critical section barriers are prepared for the weakest RMO memory model.
    4652 */
    47 #define CS_ENTER_BARRIER()                              \
    48         asm volatile (                                  \
    49                 "membar #LoadLoad | #LoadStore\n"       \
    50                 ::: "memory"                            \
    51         )
    52 #define CS_LEAVE_BARRIER()                              \
    53         asm volatile (                                  \
    54                 "membar #StoreStore\n"                  \
    55                 "membar #LoadStore\n"                   \
    56                 ::: "memory"                            \
     53#define CS_ENTER_BARRIER() \
     54        asm volatile ( \
     55                "membar #LoadLoad | #LoadStore\n" \
     56                ::: "memory" \
    5757        )
    5858
    59 #define memory_barrier()        \
    60         asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
    61 #define read_barrier()          \
    62         asm volatile ("membar #LoadLoad\n" ::: "memory")
    63 #define write_barrier()         \
    64         asm volatile ("membar #StoreStore\n" ::: "memory")
     59#define CS_LEAVE_BARRIER() \
     60        asm volatile ( \
     61                "membar #StoreStore\n" \
     62                "membar #LoadStore\n" \
     63                ::: "memory" \
     64        )
    6565
    66 #define flush(a)                \
    67         asm volatile ("flush %0\n" :: "r" ((a)) : "memory")
     66#define memory_barrier() \
     67        asm volatile ( \
     68                "membar #LoadLoad | #StoreStore\n" \
     69                ::: "memory" \
     70        )
     71
     72#define read_barrier() \
     73        asm volatile ( \
     74                "membar #LoadLoad\n" \
     75                ::: "memory" \
     76        )
     77
     78#define write_barrier() \
     79        asm volatile ( \
     80                "membar #StoreStore\n" \
     81                ::: "memory" \
     82        )
     83
     84#define flush(a) \
     85        asm volatile ( \
     86                "flush %[reg]\n" \
     87                :: [reg] "r" ((a)) \
     88                : "memory" \
     89        )
    6890
    6991/** Flush Instruction pipeline. */
    70 static inline void flush_pipeline(void)
     92NO_TRACE static inline void flush_pipeline(void)
    7193{
    7294        uint64_t pc;
    73 
     95       
    7496        /*
    7597         * The FLUSH instruction takes address parameter.
    … …  
    80102         * the %pc register will always be in the range mapped by
    81103         * DTLB.
     104         *
    82105         */
    83          
    84         asm volatile (
    85                 "rd %%pc, %0\n"
    86                 "flush %0\n"
    87                 : "=&r" (pc)
     106       
     107        asm volatile (
     108                "rd %%pc, %[pc]\n"
     109                "flush %[pc]\n"
     110                : [pc] "=&r" (pc)
    88111        );
    89112}
    90113
    91114/** Memory Barrier instruction. */
    92 static inline void membar(void)
     115NO_TRACE static inline void membar(void)
    93116{
    94         asm volatile ("membar #Sync\n");
     117        asm volatile (
     118                "membar #Sync\n"
     119        );
    95120}
    96121
    97122#if defined (US)
    98123
    99 #define smc_coherence(a)        \
    100 {                               \
    101         write_barrier();        \
    102         flush((a));             \
    103 }
     124#define FLUSH_INVAL_MIN  4
    104125
    105 #define FLUSH_INVAL_MIN         4
    106 #define smc_coherence_block(a, l)                       \
    107 {                                                       \
    108         unsigned long i;                                \
    109         write_barrier();                                \
    110         for (i = 0; i < (l); i += FLUSH_INVAL_MIN)      \
    111                 flush((void *)(a) + i);                 \
    112 }
     126#define smc_coherence(a) \
     127        do { \
     128                write_barrier(); \
     129                flush((a)); \
     130        } while (0)
     131
     132#define smc_coherence_block(a, l) \
     133        do { \
     134                unsigned long i; \
     135                write_barrier(); \
     136                \
     137                for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \
     138                        flush((void *)(a) + i); \
     139        } while (0)
    113140
    114141#elif defined (US3)
    115142
    116 #define smc_coherence(a)        \
    117 {                               \
    118         write_barrier();        \
    119         flush_pipeline();       \
    120 }
     143#define smc_coherence(a) \
     144        do { \
     145                write_barrier(); \
     146                flush_pipeline(); \
     147        } while (0)
    121148
    122 #define smc_coherence_block(a, l)       \
    123 {                                       \
    124         write_barrier();                \
    125         flush_pipeline();               \
    126 }
     149#define smc_coherence_block(a, l) \
     150        do { \
     151                write_barrier(); \
     152                flush_pipeline(); \
     153        } while (0)
    127154
    128 #endif  /* defined(US3) */
     155#endif  /* defined(US3) */
    129156
    130157#endif

  • kernel/arch/sparc64/include/cycle.h

    re3ee9b9 r7a0359b  
    3636#define KERN_sparc64_CYCLE_H_
    3737
    38 #include <arch/asm.h>
     38#include <arch/asm.h>
     39#include <trace.h>
    3940
    40 static inline uint64_t get_cycle(void)
     41NO_TRACE static inline uint64_t get_cycle(void)
    4142{
    4243        return tick_read();

  • kernel/arch/sparc64/include/faddr.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    3838#include <typedefs.h>
    3939
    40 #define FADDR(fptr)             ((uintptr_t) (fptr))
     40#define FADDR(fptr)  ((uintptr_t) (fptr))
    4141
    4242#endif

  • kernel/arch/sparc64/include/interrupt.h

    re3ee9b9 r7a0359b  
    3939#include <typedefs.h>
    4040#include <arch/regdef.h>
     41#include <trace.h>
    4142
    42 #define IVT_ITEMS       15
    43 #define IVT_FIRST       1
     43#define IVT_ITEMS  15
     44#define IVT_FIRST  1
    4445
    4546/* This needs to be defined for inter-architecture API portability. */
    46 #define VECTOR_TLB_SHOOTDOWN_IPI        0
     47#define VECTOR_TLB_SHOOTDOWN_IPI  0
    4748
    4849enum {
    4950        IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI
    50 };             
     51};
    5152
    5253typedef struct istate {
    53         uint64_t        tnpc;
    54         uint64_t        tpc;
    55         uint64_t        tstate;
     54        uint64_t tnpc;
     55        uint64_t tpc;
     56        uint64_t tstate;
    5657} istate_t;
    5758
    58 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     59NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     60    uintptr_t retaddr)
    5961{
    6062        istate->tpc = retaddr;
    6163}
    6264
    63 static inline int istate_from_uspace(istate_t *istate)
     65NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    6466{
    6567        return !(istate->tstate & TSTATE_PRIV_BIT);
    6668}
    6769
    68 static inline unative_t istate_get_pc(istate_t *istate)
     70NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    6971{
    7072        return istate->tpc;
    7173}
    7274
    73 static inline unative_t istate_get_fp(istate_t *istate)
     75NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    7476{
    75         return 0;       /* TODO */
     77        /* TODO */
     78       
     79        return 0;
    7680}
    7781

  • kernel/arch/sparc64/include/mm/as.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */
    … …  
    3737
    3838#if defined (SUN4U)
     39
    3940#include <arch/mm/sun4u/as.h>
     41
    4042#elif defined (SUN4V)
     43
    4144#include <arch/mm/sun4v/as.h>
     45
    4246#endif
    4347

  • kernel/arch/sparc64/include/mm/frame.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */
    … …  
    3737
    3838#if defined (SUN4U)
     39
    3940#include <arch/mm/sun4u/frame.h>
     41
    4042#elif defined (SUN4V)
     43
    4144#include <arch/mm/sun4v/frame.h>
     45
    4246#endif
    4347

  • kernel/arch/sparc64/include/mm/sun4u/tlb.h

    re3ee9b9 r7a0359b  
    100100#include <arch/barrier.h>
    101101#include <typedefs.h>
     102#include <trace.h>
    102103#include <arch/register.h>
    103104#include <arch/cpu.h>
    … …  
    242243 * Determine the number of entries in the DMMU's small TLB.
    243244 */
    244 static inline uint16_t tlb_dsmall_size(void)
     245NO_TRACE static inline uint16_t tlb_dsmall_size(void)
    245246{
    246247        return 16;
    … …  
    250251 * Determine the number of entries in each DMMU's big TLB.
    251252 */
    252 static inline uint16_t tlb_dbig_size(void)
     253NO_TRACE static inline uint16_t tlb_dbig_size(void)
    253254{
    254255        return 512;
    … …  
    258259 * Determine the number of entries in the IMMU's small TLB.
    259260 */
    260 static inline uint16_t tlb_ismall_size(void)
     261NO_TRACE static inline uint16_t tlb_ismall_size(void)
    261262{
    262263        return 16;
    … …  
    266267 * Determine the number of entries in the IMMU's big TLB.
    267268 */
    268 static inline uint16_t tlb_ibig_size(void)
     269NO_TRACE static inline uint16_t tlb_ibig_size(void)
    269270{
    270271        if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
    … …  
    280281 * @return              Current value of Primary Context Register.
    281282 */
    282 static inline uint64_t mmu_primary_context_read(void)
     283NO_TRACE static inline uint64_t mmu_primary_context_read(void)
    283284{
    284285        return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
    … …  
    289290 * @param v             New value of Primary Context Register.
    290291 */
    291 static inline void mmu_primary_context_write(uint64_t v)
     292NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
    292293{
    293294        asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    … …  
    299300 * @return              Current value of Secondary Context Register.
    300301 */
    301 static inline uint64_t mmu_secondary_context_read(void)
     302NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
    302303{
    303304        return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
    … …  
    308309 * @param v             New value of Primary Context Register.
    309310 */
    310 static inline void mmu_secondary_context_write(uint64_t v)
     311NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
    311312{
    312313        asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    … …  
    323324 *                      Register.
    324325 */
    325 static inline uint64_t itlb_data_access_read(size_t entry)
     326NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)
    326327{
    327328        itlb_data_access_addr_t reg;
    … …  
    337338 * @param value         Value to be written.
    338339 */
    339 static inline void itlb_data_access_write(size_t entry, uint64_t value)
     340NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)
    340341{
    341342        itlb_data_access_addr_t reg;
    … …  
    354355 *                      Register.
    355356 */
    356 static inline uint64_t dtlb_data_access_read(size_t entry)
     357NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)
    357358{
    358359        dtlb_data_access_addr_t reg;
    … …  
    368369 * @param value         Value to be written.
    369370 */
    370 static inline void dtlb_data_access_write(size_t entry, uint64_t value)
     371NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)
    371372{
    372373        dtlb_data_access_addr_t reg;
    … …  
    384385 * @return              Current value of specified IMMU TLB Tag Read Register.
    385386 */
    386 static inline uint64_t itlb_tag_read_read(size_t entry)
     387NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)
    387388{
    388389        itlb_tag_read_addr_t tag;
    … …  
    399400 * @return              Current value of specified DMMU TLB Tag Read Register.
    400401 */
    401 static inline uint64_t dtlb_tag_read_read(size_t entry)
     402NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)
    402403{
    403404        dtlb_tag_read_addr_t tag;
    … …  
    419420 *                      Register.
    420421 */
    421 static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
     422NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
    422423{
    423424        itlb_data_access_addr_t reg;
    … …  
    434435 * @param value         Value to be written.
    435436 */
    436 static inline void itlb_data_access_write(int tlb, size_t entry,
     437NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
    437438        uint64_t value)
    438439{
    … …  
    454455 *                      Register.
    455456 */
    456 static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
     457NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
    457458{
    458459        dtlb_data_access_addr_t reg;
    … …  
    470471 * @param value         Value to be written.
    471472 */
    472 static inline void dtlb_data_access_write(int tlb, size_t entry,
     473NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
    473474        uint64_t value)
    474475{
    … …  
    489490 * @return              Current value of specified IMMU TLB Tag Read Register.
    490491 */
    491 static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
     492NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
    492493{
    493494        itlb_tag_read_addr_t tag;
    … …  
    506507 * @return              Current value of specified DMMU TLB Tag Read Register.
    507508 */
    508 static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
     509NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
    509510{
    510511        dtlb_tag_read_addr_t tag;
    … …  
    523524 * @param v             Value to be written.
    524525 */
    525 static inline void itlb_tag_access_write(uint64_t v)
     526NO_TRACE static inline void itlb_tag_access_write(uint64_t v)
    526527{
    527528        asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    … …  
    533534 * @return              Current value of IMMU TLB Tag Access Register.
    534535 */
    535 static inline uint64_t itlb_tag_access_read(void)
     536NO_TRACE static inline uint64_t itlb_tag_access_read(void)
    536537{
    537538        return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
    … …  
    542543 * @param v             Value to be written.
    543544 */
    544 static inline void dtlb_tag_access_write(uint64_t v)
     545NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)
    545546{
    546547        asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    … …  
    552553 * @return              Current value of DMMU TLB Tag Access Register.
    553554 */
    554 static inline uint64_t dtlb_tag_access_read(void)
     555NO_TRACE static inline uint64_t dtlb_tag_access_read(void)
    555556{
    556557        return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
    … …  
    562563 * @param v             Value to be written.
    563564 */
    564 static inline void itlb_data_in_write(uint64_t v)
     565NO_TRACE static inline void itlb_data_in_write(uint64_t v)
    565566{
    566567        asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    … …  
    572573 * @param v             Value to be written.
    573574 */
    574 static inline void dtlb_data_in_write(uint64_t v)
     575NO_TRACE static inline void dtlb_data_in_write(uint64_t v)
    575576{
    576577        asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    … …  
    582583 * @return              Current content of I-SFSR register.
    583584 */
    584 static inline uint64_t itlb_sfsr_read(void)
     585NO_TRACE static inline uint64_t itlb_sfsr_read(void)
    585586{
    586587        return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
    … …  
    591592 * @param v             New value of I-SFSR register.
    592593 */
    593 static inline void itlb_sfsr_write(uint64_t v)
     594NO_TRACE static inline void itlb_sfsr_write(uint64_t v)
    594595{
    595596        asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    … …  
    601602 * @return              Current content of D-SFSR register.
    602603 */
    603 static inline uint64_t dtlb_sfsr_read(void)
     604NO_TRACE static inline uint64_t dtlb_sfsr_read(void)
    604605{
    605606        return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
    … …  
    610611 * @param v             New value of D-SFSR register.
    611612 */
    612 static inline void dtlb_sfsr_write(uint64_t v)
     613NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)
    613614{
    614615        asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    … …  
    620621 * @return              Current content of D-SFAR register.
    621622 */
    622 static inline uint64_t dtlb_sfar_read(void)
     623NO_TRACE static inline uint64_t dtlb_sfar_read(void)
    623624{
    624625        return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
    … …  
    633634 * @param page          Address which is on the page to be demapped.
    634635 */
    635 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
     636NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
    636637{
    637638        tlb_demap_addr_t da;
    … …  
    659660 * @param page          Address which is on the page to be demapped.
    660661 */
    661 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
     662NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
    662663{
    663664        tlb_demap_addr_t da;

  • kernel/arch/sparc64/include/mm/sun4v/tlb.h

    re3ee9b9 r7a0359b  
    4343
    4444#include <arch/mm/tte.h>
    45 #include <print.h>
     45#include <trace.h>
    4646#include <arch/mm/mmu.h>
    4747#include <arch/mm/page.h>
    … …  
    8888 * @return      Current value of Primary Context Register.
    8989 */
    90 static inline uint64_t mmu_primary_context_read(void)
     90NO_TRACE static inline uint64_t mmu_primary_context_read(void)
    9191{
    9292        return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG);
    9393}
    94  
     94
    9595/** Write MMU Primary Context Register.
    9696 *
    9797 * @param v     New value of Primary Context Register.
    9898 */
    99 static inline void mmu_primary_context_write(uint64_t v)
     99NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
    100100{
    101101        asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v);
    102102}
    103  
     103
    104104/** Read MMU Secondary Context Register.
    105105 *
    106106 * @return      Current value of Secondary Context Register.
    107107 */
    108 static inline uint64_t mmu_secondary_context_read(void)
     108NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
    109109{
    110110        return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG);
    111111}
    112  
     112
    113113/** Write MMU Secondary Context Register.
    114114 *
    115115 * @param v     New value of Secondary Context Register.
    116116 */
    117 static inline void mmu_secondary_context_write(uint64_t v)
     117NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
    118118{
    119119        asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v);
    … …  
    126126 * @param mmu_flag      MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
    127127 */
    128 static inline void mmu_demap_ctx(int context, int mmu_flag) {
     128NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag) {
    129129        __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
    130130}
    … …  
    137137 * @param mmu_flag      MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
    138138 */
    139 static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
     139NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
    140140        __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
    141141}

  • kernel/arch/sparc64/include/mm/tlb.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */
    … …  
    3636#define KERN_sparc64_TLB_H_
    3737
     38#if defined (SUN4U)
    3839
    39 #if defined (SUN4U)
    4040#include <arch/mm/sun4u/tlb.h>
     41
    4142#elif defined (SUN4V)
     43
    4244#include <arch/mm/sun4v/tlb.h>
     45
    4346#endif
    4447

  • kernel/arch/sparc64/include/sun4u/asm.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    3636#define KERN_sparc64_sun4u_ASM_H_
    3737
    38 extern uint64_t read_from_ag_g7(void);
    39 extern void write_to_ag_g6(uint64_t val);
    40 extern void write_to_ag_g7(uint64_t val);
    41 extern void write_to_ig_g6(uint64_t val);
    42 
     38#include <trace.h>
    4339
    4440/** Read Version Register.
    4541 *
    4642 * @return Value of VER register.
     43 *
    4744 */
    48 static inline uint64_t ver_read(void)
     45NO_TRACE static inline uint64_t ver_read(void)
    4946{
    5047        uint64_t v;
    5148       
    52         asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
     49        asm volatile (
     50                "rdpr %%ver, %[v]\n"
     51                : [v] "=r" (v)
     52        );
    5353       
    5454        return v;
    5555}
     56
     57extern uint64_t read_from_ag_g7(void);
     58extern void write_to_ag_g6(uint64_t);
     59extern void write_to_ag_g7(uint64_t);
     60extern void write_to_ig_g6(uint64_t);
    5661
    5762#endif

  • kernel/arch/sparc64/include/sun4u/cpu.h

    re3ee9b9 r7a0359b  
    3636#define KERN_sparc64_sun4u_CPU_H_
    3737
    38 #define MANUF_FUJITSU           0x04
    39 #define MANUF_ULTRASPARC        0x17    /**< UltraSPARC I, UltraSPARC II */
    40 #define MANUF_SUN               0x3e
     38#define MANUF_FUJITSU     0x04
     39#define MANUF_ULTRASPARC  0x17  /**< UltraSPARC I, UltraSPARC II */
     40#define MANUF_SUN         0x3e
    4141
    42 #define IMPL_ULTRASPARCI        0x10
    43 #define IMPL_ULTRASPARCII       0x11
    44 #define IMPL_ULTRASPARCII_I     0x12
    45 #define IMPL_ULTRASPARCII_E     0x13
    46 #define IMPL_ULTRASPARCIII      0x14
    47 #define IMPL_ULTRASPARCIII_PLUS 0x15
    48 #define IMPL_ULTRASPARCIII_I    0x16
    49 #define IMPL_ULTRASPARCIV       0x18
    50 #define IMPL_ULTRASPARCIV_PLUS  0x19
     42#define IMPL_ULTRASPARCI         0x10
     43#define IMPL_ULTRASPARCII        0x11
     44#define IMPL_ULTRASPARCII_I      0x12
     45#define IMPL_ULTRASPARCII_E      0x13
     46#define IMPL_ULTRASPARCIII       0x14
     47#define IMPL_ULTRASPARCIII_PLUS  0x15
     48#define IMPL_ULTRASPARCIII_I     0x16
     49#define IMPL_ULTRASPARCIV        0x18
     50#define IMPL_ULTRASPARCIV_PLUS   0x19
    5151
    52 #define IMPL_SPARC64V           0x5
     52#define IMPL_SPARC64V  0x5
    5353
    5454#ifndef __ASM__
    … …  
    5858#include <arch/regdef.h>
    5959#include <arch/asm.h>
     60#include <trace.h>
    6061
    6162#ifdef CONFIG_SMP
    … …  
    6465
    6566typedef struct {
    66         uint32_t mid;                   /**< Processor ID as read from
    67                                              UPA_CONFIG/FIREPLANE_CONFIG. */
     67        uint32_t mid;              /**< Processor ID as read from
     68                                        UPA_CONFIG/FIREPLANE_CONFIG. */
    6869        ver_reg_t ver;
    69         uint32_t clock_frequency;       /**< Processor frequency in Hz. */
    70         uint64_t next_tick_cmpr;        /**< Next clock interrupt should be
    71                                              generated when the TICK register
    72                                              matches this value. */
     70        uint32_t clock_frequency;  /**< Processor frequency in Hz. */
     71        uint64_t next_tick_cmpr;   /**< Next clock interrupt should be
     72                                        generated when the TICK register
     73                                        matches this value. */
    7374} cpu_arch_t;
    7475
    75 
    76 /**
    77  * Reads the module ID (agent ID/CPUID) of the current CPU.
     76/** Read the module ID (agent ID/CPUID) of the current CPU.
     77 *
    7878 */
    79 static inline uint32_t read_mid(void)
     79NO_TRACE static inline uint32_t read_mid(void)
    8080{
    8181        uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
    8282        icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
     83       
    8384#if defined (US)
    8485        return icbus_config & 0x1f;
    … …  
    9192}
    9293
    93 #endif 
     94#endif
    9495
    9596#endif

  • kernel/arch/sparc64/include/sun4v/asm.h

    re3ee9b9 r7a0359b  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/sun4v/cpu.h

    re3ee9b9 r7a0359b  
    3737
    3838/** Maximum number of virtual processors. */
    39 #define MAX_NUM_STRANDS         64
     39#define MAX_NUM_STRANDS  64
    4040
    4141/** Maximum number of logical processors in a processor core */
    42 #define MAX_CORE_STRANDS        8
     42#define MAX_CORE_STRANDS  8
    4343
    4444#ifndef __ASM__
    … …  
    5959
    6060typedef struct cpu_arch {
    61         uint64_t id;                    /**< virtual processor ID */
    62         uint32_t clock_frequency;       /**< Processor frequency in Hz. */
    63         uint64_t next_tick_cmpr;        /**< Next clock interrupt should be
    64                                              generated when the TICK register
    65                                              matches this value. */
    66         exec_unit_t *exec_unit;         /**< Physical core. */
    67         unsigned long proposed_nrdy;    /**< Proposed No. of ready threads
    68                                              so that cores are equally balanced. */
     61        uint64_t id;                  /**< virtual processor ID */
     62        uint32_t clock_frequency;     /**< Processor frequency in Hz. */
     63        uint64_t next_tick_cmpr;      /**< Next clock interrupt should be
     64                                           generated when the TICK register
     65                                           matches this value. */
     66        exec_unit_t *exec_unit;       /**< Physical core. */
     67        unsigned long proposed_nrdy;  /**< Proposed No. of ready threads
     68                                           so that cores are equally balanced. */
    6969} cpu_arch_t;
    70 
    71 #endif 
    72 
    73 #ifdef __ASM__
    7470
    7571#endif
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