- Timestamp:
- 2005-07-15T21:57:30Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- b4a4c5e3
- Parents:
- e41c47e
- Location:
- arch/ia32
- Files:
-
- 22 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia32/boot/boot.S
re41c47e r76cec1e 51 51 xorw %ax,%ax # reset, %al will be used below 52 52 movw %ax,%dx # fd0, %dh and %dl will be used below 53 53 movw %dx,%ds 54 54 55 55 movw %dx,%ss # initialize stack … … 59 59 jc stop_trying 60 60 61 61 movw %dx,%ds 62 62 movw %dx,%ss 63 63 movw $0x7c00,%sp … … 93 93 movw logical_sector,%ax 94 94 divb sectors 95 95 96 96 movb %ah,%cl 97 98 97 incb %cl # sector 98 99 99 movb %al,%ch 100 100 shrb $1,%ch # track 101 101 102 102 movb %al,%dh 103 103 andb $1,%dh # head … … 127 127 movw %sp,%bp 128 128 pusha 129 129 130 130 movb $0xe,%ah 131 131 movb $7,%bl 132 132 int $0x10 133 133 134 134 popa 135 135 pop %bp -
arch/ia32/boot/boot.ld
re41c47e r76cec1e 1 1 OUTPUT_FORMAT(binary) 2 2 SECTIONS { 3 3 .text 0x7c00 : AT (0x0) { *(.text) } 4 4 } -
arch/ia32/include/cpu.h
re41c47e r76cec1e 43 43 44 44 struct cpu_arch { 45 46 47 48 45 int vendor; 46 int family; 47 int model; 48 int stepping; 49 49 struct tss *tss; 50 50 }; -
arch/ia32/src/acpi/acpi.c
re41c47e r76cec1e 85 85 void acpi_init(void) 86 86 { 87 88 87 __u8 *addr[2] = { NULL, (__u8 *) 0xe0000 }; 88 int i, j, length[2] = { 1024, 128*1024 }; 89 89 __u64 *sig = (__u64 *) RSDP_SIGNATURE; 90 90 91 91 /* 92 92 * Find Root System Description Pointer 93 94 95 93 * 1. search first 1K of EBDA 94 * 2. search 128K starting at 0xe0000 95 */ 96 96 97 97 addr[0] = (__u8 *) ebda; 98 98 for (i = (ebda ? 0 : 1); i < 2; i++) { 99 100 101 102 103 104 105 99 for (j = 0; j < length[i]; j += 16) { 100 if (*((__u64 *) &addr[i][j]) == *sig && rsdp_check(&addr[i][j])) { 101 acpi_rsdp = (struct acpi_rsdp *) &addr[i][j]; 102 goto rsdp_found; 103 } 104 } 105 } 106 106 107 107 return; 108 108 109 109 rsdp_found: 110 111 110 printf("%L: ACPI Root System Description Pointer\n", acpi_rsdp); 111 112 112 acpi_rsdt = (struct acpi_rsdt *) acpi_rsdp->rsdt_address; 113 113 if (acpi_rsdp->revision) acpi_xsdt = (struct acpi_xsdt *) ((__address) acpi_rsdp->xsdt_address); … … 138 138 struct acpi_sdt_header *h = (struct acpi_sdt_header *) acpi_rsdt->entry[i]; 139 139 140 140 map_sdt(h); 141 141 if (*((__u32 *) &h->signature[0])==*((__u32 *) &signature_map[j].signature[0])) { 142 142 if (!acpi_sdt_check((__u8 *) h)) -
arch/ia32/src/asm.s
re41c47e r76cec1e 96 96 push %ds 97 97 push %es 98 98 99 99 # we must fill the data segment registers 100 100 movw $16,%ax 101 101 movw %ax,%ds 102 102 movw %ax,%es 103 103 104 104 movl $(\i),%edi 105 105 pushl %ebp … … 114 114 popa 115 115 pop %ebp 116 117 118 116 117 iret 118 119 119 .if (\n-\i)-1 120 120 handler "(\i+1)",\n … … 180 180 movl %esp,%ebp 181 181 pusha 182 182 183 183 movl 8(%ebp),%edx 184 184 movl 12(%ebp),%eax 185 185 outb %al,%dx 186 186 187 187 popa 188 188 pop %ebp … … 198 198 movl %esp,%ebp 199 199 pusha 200 200 201 201 movl 8(%ebp),%edx 202 202 movl 12(%ebp),%eax 203 203 outw %ax,%dx 204 204 205 205 popa 206 206 pop %ebp … … 216 216 movl %esp,%ebp 217 217 pusha 218 218 219 219 movl 8(%ebp),%edx 220 220 movl 12(%ebp),%eax 221 221 outl %eax,%dx 222 222 223 223 popa 224 224 pop %ebp … … 240 240 movl %esp,%ebp 241 241 pusha 242 242 243 243 cld 244 244 movl CNT(%ebp),%ecx 245 245 movl DST(%ebp),%edi 246 movl SRC(%ebp),%esi 247 246 movl SRC(%ebp),%esi 247 248 248 rep movsb %ds:(%esi),%es:(%edi) 249 249 250 250 popa 251 251 pop %ebp … … 266 266 movl %esp,%ebp 267 267 pusha 268 268 269 269 cld 270 270 movl CNT(%ebp),%ecx 271 271 movl DST(%ebp),%edi 272 272 movl X(%ebp),%eax 273 273 274 274 rep stosb %al,%es:(%edi) 275 276 275 276 popa 277 277 pop %ebp 278 278 ret … … 292 292 movl %esp,%ebp 293 293 pusha 294 294 295 295 cld 296 296 movl CNT(%ebp),%ecx 297 297 movl DST(%ebp),%edi 298 298 movl X(%ebp),%eax 299 299 300 300 rep stosw %ax,%es:(%edi) 301 302 301 302 popa 303 303 pop %ebp 304 304 ret … … 321 321 322 322 pusha 323 323 324 324 cld 325 325 movl CNT(%ebp),%ecx 326 326 movl DST(%ebp),%edi 327 movl SRC(%ebp),%esi 328 327 movl SRC(%ebp),%esi 328 329 329 repe cmpsb %es:(%edi),%ds:(%esi) 330 330 movl %ecx,(%ebp) -
arch/ia32/src/boot/boot.S
re41c47e r76cec1e 57 57 movw %ax,%fs 58 58 movw %ax,%ds # kernel data + stack 59 59 movw %ax,%ss 60 60 movl $0x7c00,%esp 61 61 -
arch/ia32/src/context.s
re41c47e r76cec1e 43 43 movl 4(%esp),%eax # the caller's return %eip 44 44 movl 8(%esp),%ebx # address of the kernel_context variable to save context to 45 45 movl %eax,4(%ebx) # %eip -> ctx->pc 46 46 movl %esp,(%ebx) # %esp -> ctx->sp 47 47 … … 54 54 movl %esi,20(%eax) 55 55 movl %edi,24(%eax) 56 movl %ebp,28(%eax) 57 56 movl %ebp,28(%eax) 57 58 58 xorl %eax,%eax # context_save returns 1 59 59 incl %eax … … 65 65 # Restore CPU context from the kernel_context variable 66 66 # pointed by the 1st argument. Returns 0 in EAX. 67 # 67 # 68 68 context_restore: 69 69 movl 4(%esp),%eax # address of the kernel_context variable to restore context from … … 80 80 movl 4(%eax),%eax 81 81 movl %eax,(%esp) # ctx->pc -> saver's return %eip 82 82 xorl %eax,%eax # context_restore returns 0 83 83 ret -
arch/ia32/src/cpu/cpu.c
re41c47e r76cec1e 109 109 * Check for AMD processor. 110 110 */ 111 if (info.cpuid_ebx==AMD_CPUID_EBX && 112 info.cpuid_ecx==AMD_CPUID_ECX && 113 info.cpuid_edx==AMD_CPUID_EDX) { 114 111 if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { 115 112 CPU->arch.vendor = VendorAMD; 116 113 } … … 119 116 * Check for Intel processor. 120 117 */ 121 if (info.cpuid_ebx==INTEL_CPUID_EBX && 122 info.cpuid_ecx==INTEL_CPUID_ECX && 123 info.cpuid_edx==INTEL_CPUID_EDX) { 124 118 if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { 125 119 CPU->arch.vendor = VendorIntel; 126 127 120 } 128 121 -
arch/ia32/src/cpuid.s
re41c47e r76cec1e 84 84 movl %ecx,8(%esi) 85 85 movl %edx,12(%esi) 86 86 87 87 popa 88 88 popl %ebp -
arch/ia32/src/drivers/ega.c
re41c47e r76cec1e 70 70 { 71 71 if (ega_cursor < SCREEN) 72 72 return; 73 73 74 74 memcopy(PA2KA(VIDEORAM) + ROW*2, PA2KA(VIDEORAM), (SCREEN - ROW)*2); … … 86 86 switch (ch) { 87 87 case '\n': 88 89 88 ega_cursor = (ega_cursor + ROW) - ega_cursor % ROW; 89 break; 90 90 case '\t': 91 92 91 ega_cursor = (ega_cursor + 8) - ega_cursor % 8; 92 break; 93 93 default: 94 95 96 94 ega_display_char(ch); 95 ega_cursor++; 96 break; 97 97 } 98 98 ega_check_cursor(); 99 99 ega_move_cursor(); 100 100 101 101 spinlock_unlock(&egalock); 102 102 cpu_priority_restore(pri); -
arch/ia32/src/drivers/i8254.c
re41c47e r76cec1e 84 84 85 85 do { 86 86 /* will read both status and count */ 87 87 outb(CLK_PORT4, 0xc2); 88 88 not_ok = (inb(CLK_PORT1)>>6)&1; … … 110 110 o2 |= inb(CLK_PORT1) << 8; 111 111 112 113 CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + 114 (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0); 115 112 CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0); 116 113 117 114 clk1 = rdtsc(); -
arch/ia32/src/drivers/i8259.c
re41c47e r76cec1e 45 45 /* ICW2: IRQ 0 maps to INT IRQBASE */ 46 46 outb(PIC_PIC0PORT2, IVT_IRQBASE); 47 47 48 48 /* ICW3: pic1 using IRQ IRQ_PIC1 */ 49 49 outb(PIC_PIC0PORT2, 1 << IRQ_PIC1); 50 51 /* ICW4: i8086 mode */ 50 51 /* ICW4: i8086 mode */ 52 52 outb(PIC_PIC0PORT2, 1); 53 53 … … 55 55 outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4); 56 56 57 /* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */ 57 /* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */ 58 58 outb(PIC_PIC1PORT2, IVT_IRQBASE + 8); 59 59 … … 61 61 outb(PIC_PIC1PORT2, PIC_PIC1ID); 62 62 63 /* ICW4: i8086 mode */ 63 /* ICW4: i8086 mode */ 64 64 outb(PIC_PIC1PORT2, 1); 65 65 … … 76 76 disable_irqs_function = pic_disable_irqs; 77 77 eoi_function = pic_eoi; 78 78 79 79 pic_disable_irqs(0xffff); /* disable all irq's */ 80 80 pic_enable_irqs(1<<IRQ_PIC1); /* but enable pic1 */ … … 84 84 { 85 85 __u8 x; 86 86 87 87 if (irqmask & 0xff) { 88 88 x = inb(PIC_PIC0PORT2); 89 89 outb(PIC_PIC0PORT2, x & (~(irqmask & 0xff))); 90 90 } 91 91 if (irqmask >> 8) { 92 92 x = inb(PIC_PIC1PORT2); 93 93 outb(PIC_PIC1PORT2, x & (~(irqmask >> 8))); 94 94 } … … 98 98 { 99 99 __u8 x; 100 100 101 101 if (irqmask & 0xff) { 102 102 x = inb(PIC_PIC0PORT2); 103 103 outb(PIC_PIC0PORT2, x | (irqmask & 0xff)); 104 104 } 105 105 if (irqmask >> 8) { 106 106 x = inb(PIC_PIC1PORT2); 107 107 outb(PIC_PIC1PORT2, x | (irqmask >> 8)); 108 108 } … … 112 112 { 113 113 outb(0x20,0x20); 114 114 outb(0xa0,0x20); 115 115 } 116 116 -
arch/ia32/src/fpu_context.c
re41c47e r76cec1e 79 79 { 80 80 asm( 81 81 "fninit;" 82 82 ); 83 83 } -
arch/ia32/src/ia32.c
re41c47e r76cec1e 56 56 bios_init(); 57 57 i8042_init(); /* a20 bit */ 58 58 i8259_init(); /* PIC */ 59 59 i8254_init(); /* hard clock */ 60 60 -
arch/ia32/src/interrupt.c
re41c47e r76cec1e 98 98 { 99 99 reset_TS_flag(); 100 if ((CPU->fpu_owner)!=NULL) 101 { 102 fpu_lazy_context_save(&((CPU->fpu_owner)->saved_fpu_context)); 100 if ((CPU->fpu_owner)!=NULL) { 101 fpu_lazy_context_save(&((CPU->fpu_owner)->saved_fpu_context)); 103 102 (CPU->fpu_owner)->fpu_context_engaged=0; /* don't prevent migration */ 104 103 } 105 104 if(THREAD->fpu_context_exists) fpu_lazy_context_restore(&(THREAD->saved_fpu_context)); 106 105 else {fpu_init();THREAD->fpu_context_exists=1;} 107 106 CPU->fpu_owner=THREAD; 108 107 } -
arch/ia32/src/mm/frame.c
re41c47e r76cec1e 40 40 frame_not_free(0x0); 41 41 42 43 42 frame_region_not_free(0xa0000,0xff000); 43 frame_region_not_free(0xfec00000,0xffffffff); 44 44 } 45 45 } -
arch/ia32/src/mm/page.c
re41c47e r76cec1e 57 57 dba = frame_alloc(FRAME_KA | FRAME_PANIC); 58 58 memsetb(dba, PAGE_SIZE, 0); 59 59 60 60 bootstrap_dba = dba; 61 61 -
arch/ia32/src/pm.c
re41c47e r76cec1e 46 46 */ 47 47 struct descriptor gdt[GDT_ITEMS] = { 48 49 50 51 52 53 54 55 56 57 58 59 48 /* NULL descriptor */ 49 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 50 /* KTEXT descriptor */ 51 { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, 52 /* KDATA descriptor */ 53 { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, 54 /* UTEXT descriptor */ 55 { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, 56 /* UDATA descriptor */ 57 { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, 58 /* TSS descriptor - set up will be completed later */ 59 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 60 60 }; 61 61 … … 72 72 void gdt_setbase(struct descriptor *d, __address base) 73 73 { 74 d->base_0_15 = base & 0xffff; 75 d->base_16_23 = ((base) >> 16) & 0xff; 76 d->base_24_31 = ((base) >> 24) & 0xff; 77 74 d->base_0_15 = base & 0xffff; 75 d->base_16_23 = ((base) >> 16) & 0xff; 76 d->base_24_31 = ((base) >> 24) & 0xff; 78 77 } 79 78 80 79 void gdt_setlimit(struct descriptor *d, __u32 limit) 81 80 { 82 83 81 d->limit_0_15 = limit & 0xffff; 82 d->limit_16_19 = (limit >> 16) & 0xf; 84 83 } 85 84 … … 105 104 struct idescriptor *d; 106 105 int i; 107 106 108 107 for (i = 0; i < IDT_ITEMS; i++) { 109 108 d = &idt[i]; -
arch/ia32/src/proc/scheduler.c
re41c47e r76cec1e 35 35 { 36 36 CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-8]; 37 37 CPU->arch.tss->ss0 = selector(KDATA_DES); 38 38 } -
arch/ia32/src/smp/apic.c
re41c47e r76cec1e 85 85 86 86 if ((pin = mps_irq_to_pin(i)) != -1) 87 87 io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI); 88 88 } 89 89 … … 137 137 if ((esr>>7) & 1) 138 138 printf("Illegal Register Address\n"); 139 139 140 140 return !esr; 141 141 } -
arch/ia32/src/smp/mps.c
re41c47e r76cec1e 244 244 l_intr_entry_cnt++; 245 245 ct_l_intr_entry((struct __l_intr_entry *) cur); 246 246 cur += 8; 247 247 break; 248 248 249 249 default: 250 250 /* -
arch/ia32/src/userspace.c
re41c47e r76cec1e 47 47 48 48 __asm__ volatile ("" 49 50 51 52 53 54 55 49 "pushl %0\n" 50 "pushl %1\n" 51 "pushl %2\n" 52 "pushl %3\n" 53 "pushl %4\n" 54 "iret" 55 : : "i" (selector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+(THREAD_STACK_SIZE-1)), "r" (pri), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)); 56 56 57 57 /* Unreachable */
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