Changeset 7328ff4 in mainline for kernel/arch/sparc64


Ignore:
Timestamp:
2018-09-06T18:18:52Z (7 years ago)
Author:
Jiří Zárevúcky <jiri.zarevucky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
ffa73c6
Parents:
d51cca8
git-author:
Jiří Zárevúcky <jiri.zarevucky@…> (2018-08-13 01:29:17)
git-committer:
Jiří Zárevúcky <jiri.zarevucky@…> (2018-09-06 18:18:52)
Message:

Use builtin memory fences for kernel barriers, and convert smp_coherence() into a regular function

Location:
kernel/arch/sparc64
Files:
5 edited
1 moved

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/Makefile.inc

    rd51cca8 r7328ff4  
    7777        arch/$(KARCH)/src/proc/$(USARCH)/scheduler.c \
    7878        arch/$(KARCH)/src/proc/thread.c \
     79        arch/$(KARCH)/src/smc.c \
    7980        arch/$(KARCH)/src/trap/$(USARCH)/mmu.S \
    8081        arch/$(KARCH)/src/trap/$(USARCH)/trap_table.S \

  • kernel/arch/sparc64/include/arch/barrier.h

    rd51cca8 r7328ff4  
    3838#include <trace.h>
    3939
    40 /*
    41  * Our critical section barriers are prepared for the weakest RMO memory model.
    42  */
    43 #define CS_ENTER_BARRIER() \
    44         asm volatile ( \
    45                 "membar #LoadLoad | #LoadStore\n" \
    46                 ::: "memory" \
    47         )
    48 
    49 #define CS_LEAVE_BARRIER() \
    50         asm volatile ( \
    51                 "membar #StoreStore\n" \
    52                 "membar #LoadStore\n" \
    53                 ::: "memory" \
    54         )
    55 
    56 #define memory_barrier() \
    57         asm volatile ( \
    58                 "membar #LoadLoad | #StoreStore\n" \
    59                 ::: "memory" \
    60         )
    61 
    62 #define read_barrier() \
    63         asm volatile ( \
    64                 "membar #LoadLoad\n" \
    65                 ::: "memory" \
    66         )
    67 
    68 #define write_barrier() \
    69         asm volatile ( \
    70                 "membar #StoreStore\n" \
    71                 ::: "memory" \
    72         )
    73 
    74 #define flush(a) \
    75         asm volatile ( \
    76                 "flush %[reg]\n" \
    77                 :: [reg] "r" ((a)) \
    78                 : "memory" \
    79         )
    80 
    8140/** Flush Instruction pipeline. */
    8241NO_TRACE static inline void flush_pipeline(void)
    … …  
    11069}
    11170
    112 #ifdef KERNEL
    113 
    114 #if defined(US)
    115 
    116 #define FLUSH_INVAL_MIN  4
    117 
    118 #define smc_coherence(a, l) \
    119         do { \
    120                 unsigned long i; \
    121                 write_barrier(); \
    122                 \
    123                 for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \
    124                         flush((void *)(a) + i); \
    125         } while (0)
    126 
    127 #elif defined (US3)
    128 
    129 #define smc_coherence(a, l) \
    130         do { \
    131                 write_barrier(); \
    132                 flush_pipeline(); \
    133         } while (0)
    134 
    135 #endif  /* defined(US3) */
    136 
    137 #endif  /* KERNEL */
    138 
    13971#endif
    14072

  • kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h

    rd51cca8 r7328ff4  
    9898#include <arch/mm/page.h>
    9999#include <arch/asm.h>
     100#include <arch/barrier.h>
    100101#include <barrier.h>
    101102#include <typedefs.h>

  • kernel/arch/sparc64/src/smc.c

    rd51cca8 r7328ff4  
    2727 */
    2828
    29 /** @addtogroup mips32
    30  * @{
    31  */
    32 /** @file
    33  */
     29#include <barrier.h>
     30#include <arch/barrier.h>
    3431
    35 #ifndef KERN_mips32_BARRIER_H_
    36 #define KERN_mips32_BARRIER_H_
     32#if defined(US)
    3733
    38 /*
    39  * TODO: implement true MIPS memory barriers for macros below.
    40  */
    41 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
    42 #define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
     34#define FLUSH_INVAL_MIN  4
    4335
    44 #define memory_barrier() asm volatile ("" ::: "memory")
    45 #define read_barrier()   asm volatile ("" ::: "memory")
    46 #define write_barrier()  asm volatile ("" ::: "memory")
     36void smc_coherence(void *a, size_t l)
     37{
     38        asm volatile ("membar #StoreStore\n" ::: "memory");
    4739
    48 #ifdef KERNEL
     40        for (size_t i = 0; i < l; i += FLUSH_INVAL_MIN) {
     41                asm volatile (
     42                    "flush %[reg]\n"
     43                    :: [reg] "r" (a + i)
     44                    : "memory"
     45                );
     46        }
     47}
    4948
    50 #define smc_coherence(a, l)
     49#elif defined (US3)
    5150
    52 #endif  /* KERNEL */
    5351
    54 #endif
     52void smc_coherence(void *a, size_t l)
     53{
     54        asm volatile ("membar #StoreStore\n" ::: "memory");
    5555
    56 /** @}
    57  */
     56        flush_pipeline();
     57}
     58
     59#endif  /* defined(US3) */
     60

  • kernel/arch/sparc64/src/smp/sun4u/ipi.c

    rd51cca8 r7328ff4  
    3434
    3535#include <smp/ipi.h>
     36#include <arch/barrier.h>
    3637#include <arch/smp/sun4u/ipi.h>
    3738#include <assert.h>

  • kernel/arch/sparc64/src/trap/sun4u/interrupt.c

    rd51cca8 r7328ff4  
    3333 */
    3434
     35#include <arch/barrier.h>
    3536#include <arch/interrupt.h>
    3637#include <arch/sparc64.h>
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