Changeset 6eabb6e6 in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2006-09-13T13:16:30Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
34d9469e
Parents:
9a5b556
Message:

Support for sparc64 FPU context.

Location:
kernel/arch/sparc64/include
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/asm.h

    r9a5b556 r6eabb6e6  
    109109}
    110110
     111/** Read FPRS Register.
     112 *
     113 * @return Value of FPRS register.
     114 */
     115static inline uint64_t fprs_read(void)
     116{
     117        uint64_t v;
     118       
     119        __asm__ volatile ("rd %%fprs, %0\n" : "=r" (v));
     120       
     121        return v;
     122}
     123
     124/** Write FPRS Register.
     125 *
     126 * @param v New value of FPRS register.
     127 */
     128static inline void fprs_write(uint64_t v)
     129{
     130        __asm__ volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
     131}
     132
    111133/** Read SOFTINT Register.
    112134 *

  • kernel/arch/sparc64/include/fpu_context.h

    r9a5b556 r6eabb6e6  
    3838#include <arch/types.h>
    3939
     40#define ARCH_HAS_FPU
     41#define FPU_CONTEXT_ALIGN       8
     42
    4043struct fpu_context {
     44        uint64_t        d[32];
     45        uint64_t        fsr;
    4146};
    4247

  • kernel/arch/sparc64/include/regdef.h

    r9a5b556 r6eabb6e6  
    4444
    4545#define PSTATE_PRIV_BIT (1<<2)
     46#define PSTATE_PEF_BIT  (1<<4)
    4647
    4748#define TSTATE_PSTATE_SHIFT     8
    4849#define TSTATE_PRIV_BIT         (PSTATE_PRIV_BIT<<TSTATE_PSTATE_SHIFT)
    4950#define TSTATE_IE_BIT           (PSTATE_IE_BIT<<TSTATE_PSTATE_SHIFT)
     51#define TSTATE_PEF_BIT          (PSTATE_PEF_BIT<<TSTATE_PSTATE_SHIFT)
    5052
    5153#define TSTATE_CWP_MASK         0x1f

  • kernel/arch/sparc64/include/register.h

    r9a5b556 r6eabb6e6  
    8888        uint64_t value;
    8989        struct {
    90                 unsigned int_dis : 1;   /**< TICK_INT interrupt disabled flag. */
     90                unsigned int_dis : 1;           /**< TICK_INT interrupt disabled flag. */
    9191                uint64_t tick_cmpr : 63;        /**< Compare value for TICK interrupts. */
    9292        } __attribute__ ((packed));
    … …  
    106106typedef union softint_reg softint_reg_t;
    107107
     108/** Floating-point Registers State Register. */
     109union fprs_reg {
     110        uint64_t value;
     111        struct {
     112                uint64_t : 61;
     113                unsigned fef : 1;
     114                unsigned du : 1;
     115                unsigned dl : 1;
     116        } __attribute__ ((packed));
     117};
     118typedef union fprs_reg fprs_reg_t;
     119
    108120#endif
    109121

  • kernel/arch/sparc64/include/trap/exception.h

    r9a5b556 r6eabb6e6  
    4141#define TT_ILLEGAL_INSTRUCTION                  0x10
    4242#define TT_PRIVILEGED_OPCODE                    0x11
     43#define TT_FP_DISABLED                          0x20
    4344#define TT_DIVISION_BY_ZERO                     0x28
    4445#define TT_DATA_ACCESS_EXCEPTION                0x30
    … …  
    5758extern void illegal_instruction(int n, istate_t *istate);
    5859extern void privileged_opcode(int n, istate_t *istate);
     60extern void fp_disabled(int n, istate_t *istate);
    5961extern void division_by_zero(int n, istate_t *istate);
    6062extern void data_access_exception(int n, istate_t *istate);
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