Changeset 6eabb6e6 in mainline for kernel/arch/sparc64


Ignore:
Timestamp:
2006-09-13T13:16:30Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
34d9469e
Parents:
9a5b556
Message:

Support for sparc64 FPU context.

Location:
kernel/arch/sparc64
Files:
1 added
10 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/Makefile.inc

    r9a5b556 r6eabb6e6  
    8888        arch/$(ARCH)/src/console.c \
    8989        arch/$(ARCH)/src/context.S \
     90        arch/$(ARCH)/src/fpu_context.c \
    9091        arch/$(ARCH)/src/dummy.s \
    9192        arch/$(ARCH)/src/mm/as.c \

  • kernel/arch/sparc64/include/asm.h

    r9a5b556 r6eabb6e6  
    109109}
    110110
     111/** Read FPRS Register.
     112 *
     113 * @return Value of FPRS register.
     114 */
     115static inline uint64_t fprs_read(void)
     116{
     117        uint64_t v;
     118       
     119        __asm__ volatile ("rd %%fprs, %0\n" : "=r" (v));
     120       
     121        return v;
     122}
     123
     124/** Write FPRS Register.
     125 *
     126 * @param v New value of FPRS register.
     127 */
     128static inline void fprs_write(uint64_t v)
     129{
     130        __asm__ volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
     131}
     132
    111133/** Read SOFTINT Register.
    112134 *

  • kernel/arch/sparc64/include/fpu_context.h

    r9a5b556 r6eabb6e6  
    3838#include <arch/types.h>
    3939
     40#define ARCH_HAS_FPU
     41#define FPU_CONTEXT_ALIGN       8
     42
    4043struct fpu_context {
     44        uint64_t        d[32];
     45        uint64_t        fsr;
    4146};
    4247

  • kernel/arch/sparc64/include/regdef.h

    r9a5b556 r6eabb6e6  
    4444
    4545#define PSTATE_PRIV_BIT (1<<2)
     46#define PSTATE_PEF_BIT  (1<<4)
    4647
    4748#define TSTATE_PSTATE_SHIFT     8
    4849#define TSTATE_PRIV_BIT         (PSTATE_PRIV_BIT<<TSTATE_PSTATE_SHIFT)
    4950#define TSTATE_IE_BIT           (PSTATE_IE_BIT<<TSTATE_PSTATE_SHIFT)
     51#define TSTATE_PEF_BIT          (PSTATE_PEF_BIT<<TSTATE_PSTATE_SHIFT)
    5052
    5153#define TSTATE_CWP_MASK         0x1f

  • kernel/arch/sparc64/include/register.h

    r9a5b556 r6eabb6e6  
    8888        uint64_t value;
    8989        struct {
    90                 unsigned int_dis : 1;   /**< TICK_INT interrupt disabled flag. */
     90                unsigned int_dis : 1;           /**< TICK_INT interrupt disabled flag. */
    9191                uint64_t tick_cmpr : 63;        /**< Compare value for TICK interrupts. */
    9292        } __attribute__ ((packed));
    … …  
    106106typedef union softint_reg softint_reg_t;
    107107
     108/** Floating-point Registers State Register. */
     109union fprs_reg {
     110        uint64_t value;
     111        struct {
     112                uint64_t : 61;
     113                unsigned fef : 1;
     114                unsigned du : 1;
     115                unsigned dl : 1;
     116        } __attribute__ ((packed));
     117};
     118typedef union fprs_reg fprs_reg_t;
     119
    108120#endif
    109121

  • kernel/arch/sparc64/include/trap/exception.h

    r9a5b556 r6eabb6e6  
    4141#define TT_ILLEGAL_INSTRUCTION                  0x10
    4242#define TT_PRIVILEGED_OPCODE                    0x11
     43#define TT_FP_DISABLED                          0x20
    4344#define TT_DIVISION_BY_ZERO                     0x28
    4445#define TT_DATA_ACCESS_EXCEPTION                0x30
    … …  
    5758extern void illegal_instruction(int n, istate_t *istate);
    5859extern void privileged_opcode(int n, istate_t *istate);
     60extern void fp_disabled(int n, istate_t *istate);
    5961extern void division_by_zero(int n, istate_t *istate);
    6062extern void data_access_exception(int n, istate_t *istate);

  • kernel/arch/sparc64/src/asm.S

    r9a5b556 r6eabb6e6  
    228228
    229229.macro WRITE_ALTERNATE_REGISTER reg, bit
     230        rdpr %pstate, %g1                               ! save PSTATE.PEF
    230231        wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
    231232        mov %o0, \reg
     233        wrpr %g0, PSTATE_PRIV_BIT, %pstate
    232234        retl
    233         wrpr %g0, PSTATE_PRIV_BIT, %pstate
     235        wrpr %g1, 0, %pstate                            ! restore PSTATE.PEF
    234236.endm
    235237
    236238.macro READ_ALTERNATE_REGISTER reg, bit
     239        rdpr %pstate, %g1                               ! save PSTATE.PEF
    237240        wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
    238241        mov \reg, %o0
     242        wrpr %g0, PSTATE_PRIV_BIT, %pstate
    239243        retl
    240         wrpr %g0, PSTATE_PRIV_BIT, %pstate
     244        wrpr %g1, 0, %pstate                            ! restore PSTATE.PEF
    241245.endm
    242246

  • kernel/arch/sparc64/src/dummy.s

    r9a5b556 r6eabb6e6  
    3030
    3131.global cpu_sleep
    32 .global fpu_context_restore
    33 .global fpu_context_save
    34 .global fpu_enable
    35 .global fpu_init
    3632.global sys_tls_set
    3733
    … …  
    3935
    4036cpu_sleep:
    41 fpu_context_restore:
    42 fpu_context_save:
    43 fpu_enable:
    44 fpu_init:
    4537sys_tls_set:
    4638

  • kernel/arch/sparc64/src/trap/exception.c

    r9a5b556 r6eabb6e6  
    3838#include <interrupt.h>
    3939#include <arch/asm.h>
     40#include <arch/register.h>
    4041#include <debug.h>
    4142#include <typedefs.h>
    … …  
    8283}
    8384
     85/** Handle fp_disabled. (0x20) */
     86void fp_disabled(int n, istate_t *istate)
     87{
     88        fprs_reg_t fprs;
     89       
     90        fprs.value = fprs_read();
     91        if (!fprs.fef) {
     92                fprs.fef = true;
     93                fprs_write(fprs.value);
     94                return;
     95        }
     96
     97#ifdef CONFIG_FPU_LAZY
     98        scheduler_fpu_lazy_request();
     99#else
     100        fault_if_from_uspace(istate, "%s\n", __FUNCTION__);
     101        dump_istate(istate);
     102        panic("%s\n", __FUNCTION__);
     103#endif
     104}
     105
    84106/** Handle division_by_zero. (0x28) */
    85107void division_by_zero(int n, istate_t *istate)

  • kernel/arch/sparc64/src/trap/trap_table.S

    r9a5b556 r6eabb6e6  
    8383        PREEMPTIBLE_HANDLER privileged_opcode
    8484
     85/* TT = 0x20, TL = 0, fb_disabled handler */
     86.org trap_table + TT_FP_DISABLED*ENTRY_SIZE
     87.global fb_disabled_tl0
     88fp_disabled_tl0:
     89        PREEMPTIBLE_HANDLER fp_disabled
     90
    8591/* TT = 0x24, TL = 0, clean_window handler */
    8692.org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
    87 .global clean_window_handler_tl0
    88 clean_window_handler_tl0:
     93.global clean_window_tl0
     94clean_window_tl0:
    8995        CLEAN_WINDOW_HANDLER
    9096
    … …  
    490496/* TT = 0x24, TL > 0, clean_window handler */
    491497.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
    492 .global clean_window_handler_tl1
    493 clean_window_handler_tl1:
     498.global clean_window_tl1
     499clean_window_tl1:
    494500        CLEAN_WINDOW_HANDLER
    495501
    … …  
    689695       
    690696        wrpr %g0, 0, %tl
    691         wrpr %g0, PSTATE_PRIV_BIT, %pstate
     697        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
    692698        SAVE_GLOBALS
    693699       
    … …  
    706712
    707713        RESTORE_GLOBALS
     714        rdpr %pstate, %l1                       ! we must preserve the PEF bit
    708715        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    709716        wrpr %g0, 1, %tl
    … …  
    717724
    718725        /*
     726         * Copy PSTATE.PEF to the in-register copy of TSTATE.
     727         */
     728        and %l1, PSTATE_PEF_BIT, %l1
     729        sllx %l1, TSTATE_PSTATE_SHIFT, %l1
     730        sethi %hi(TSTATE_PEF_BIT), %g4
     731        andn %g1, %g4, %g1
     732        or %g1, %l1, %g1
     733
     734        /*
    719735         * Restore TSTATE, TPC and TNPC from saved copies.
    720736         */
    … …  
    722738        wrpr %g2, 0, %tpc
    723739        wrpr %g3, 0, %tnpc
     740
    724741
    725742        /*
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