Changeset 660e8fa in mainline for kernel/arch/arm32/include

Timestamp:

2013-01-18T20:49:35Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5fcd537, 6218d4b

Parents:

b5a3b50 (diff), a640bc1 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge arm fpu fixes.

Enable FPU coprocessor (cp10/11) access.
Test for cp10/11 access before using fpu instructions or touching fpu regs.
Move fpu instructions to single asm file instead of allowing it in kernel globally.
Add cp15 helper functions.
Add (unused) security extensions header.

Location:

kernel/arch/arm32/include

Files:

• barrier.h (modified) (2 diffs)
• cp15.h (added)
• regutils.h (modified) (1 diff)
• security_ext.h (added)

kernel/arch/arm32/include/barrier.h

@@ -39 +39 @@
 /*
  * TODO: implement true ARM memory barriers for macros below.
+ * ARMv6 introduced user access of the following commands:
+ * • Prefetch flush
+ * • Data synchronization barrier
+ * • Data memory barrier
+ * • Clean and prefetch range operations.
+ * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
  */
 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
 #define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
+#if defined PROCESSOR_ARCH_armv7_a
+/* ARMv7 uses instructions for memory barriers see ARM Architecture reference
+ * manual for details:
+ * DMB: ch. A8.8.43 page A8-376
+ * DSB: ch. A8.8.44 page A8-378
+ * See ch. A3.8.3 page A3-148 for details about memory barrier implementation
+ * and functionality on armv7 architecture.
+ */
+#define memory_barrier()  asm volatile ("dmb" ::: "memory")
+#define read_barrier()    asm volatile ("dsb" ::: "memory")
+#define write_barrier()   asm volatile ("dsb st" ::: "memory")
+#else
 #define memory_barrier()  asm volatile ("" ::: "memory")
 #define read_barrier()    asm volatile ("" ::: "memory")
 #define write_barrier()   asm volatile ("" ::: "memory")
-
+#endif
 /*
  * There are multiple ways ICache can be implemented on ARM machines. Namely
@@ -62 +80 @@
  */
 
-/* Available on both all supported arms,
+#ifdef PROCESSOR_ARCH_armv7_a
+#define smc_coherence(a) asm volatile ( "isb" ::: "memory")
+#define smc_coherence_block(a, l) smc_coherence(a)
+#else
+/* Available on all supported arms,
  * invalidates entire ICache so the written value does not matter. */
+//TODO might be PL1 only on armv5 -
 #define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
 #define smc_coherence_block(a, l) smc_coherence(a)
+#endif
 
 

kernel/arch/arm32/include/regutils.h

@@ -66 +66 @@
 
 /* ARM Processor Operation Modes */
-#define USER_MODE        0x10
-#define FIQ_MODE         0x11
-#define IRQ_MODE         0x12
-#define SUPERVISOR_MODE  0x13
-#define ABORT_MODE       0x17
-#define UNDEFINED_MODE   0x1b
-#define SYSTEM_MODE      0x1f
-
+enum {
+        USER_MODE = 0x10,
+        FIQ_MODE = 0x11,
+        IRQ_MODE = 0x12,
+        SUPERVISOR_MODE = 0x13,
+        MONITOR_MODE = 0x16,
+        ABORT_MODE = 0x17,
+        HYPERVISOR_MODE = 0x1a,
+        UNDEFINED_MODE = 0x1b,
+        SYSTEM_MODE = 0x1f,
+        MODE_MASK = 0x1f,
+};
 /* [CS]PRS manipulation macros */
 #define GEN_STATUS_READ(nm, reg) \