Changeset 5f310ec8 in mainline for kernel/arch/arm32/src/mm/tlb.c


Ignore:
Timestamp:
2015-09-16T18:52:13Z (10 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a1d636e
Parents:
996dc042
Message:

Access CP15 register 8 wrt. target architecture and implementation

CP15 register 8 controls the TLB(s).

  • Do not define macros for functionality which is not supported by the target architecture or implementation.
  • For ARM920T implementation, do not use TLBIMVA in invalidate_page().
File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/src/mm/tlb.c

    r996dc042 r5f310ec8  
    7979static inline void invalidate_page(uintptr_t page)
    8080{
     81#if defined(PROCESSOR_arm920t)
     82        ITLBIMVA_write(page);
     83        DTLBIMVA_write(page);
     84#else
    8185        //TODO: What about TLBIMVAA?
    8286        TLBIMVA_write(page);
     87#endif
    8388        /*
    8489         * "A TLB maintenance operation is only guaranteed to be complete after
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