Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision b7e41ac3862ec4904ebbd7804c921ef6d84d8a5b)
+++ boot/arch/arm32/src/mm.c	(revision 5e761f3f5b0673834135c4074edbe2f0fd8ae9c3)
@@ -37,4 +37,14 @@
 #include <arch/asm.h>
 #include <arch/mm.h>
+
+/** Disable the MMU */
+static void disable_paging(void)
+{
+	asm volatile (
+		"mrc p15, 0, r0, c1, c0, 0\n"
+		"bic r0, r0, #1\n"
+		"mcr p15, 0, r0, c1, c0, 0\n"
+	);
+}
 
 /** Check if caching can be enabled for a given memory section.
@@ -100,18 +110,4 @@
 		init_ptl0_section(&boot_pt[page], page);
 	
-	/*
-	 * Create 1:1 virtual-physical mapping in kernel space
-	 * (upper 2 GB), physical addresses start from 0.
-	 */
-	/* BeagleBoard-xM (DM37x) memory starts at 2GB border,
-	 * thus mapping only lower 2GB is not not enough.
-	 * Map entire AS 1:1 instead and hope it works. */
-	for (page = split_page; page < PTL0_ENTRIES; page++)
-#ifndef MACHINE_beagleboardxm
-		init_ptl0_section(&boot_pt[page], page - split_page);
-#else
-		init_ptl0_section(&boot_pt[page], page);
-#endif
-	
 	asm volatile (
 		"mcr p15, 0, %[pt], c2, c0, 0\n"
@@ -129,14 +125,5 @@
 		"ldr r0, =0x55555555\n"
 		"mcr p15, 0, r0, c3, c0, 0\n"
-		
-#ifdef PROCESSOR_armv7_a
-		/* Read Auxiliary control register */
-		"mrc p15, 0, r0, c1, c0, 1\n"
-		/* Mask to enable L2 cache */
-		"ldr r1, =0x00000002\n"
-		"orr r0, r0, r1\n"
-		/* Store Auxiliary control register */
-		"mrc p15, 0, r0, c1, c0, 1\n"
-#endif
+
 		/* Current settings */
 		"mrc p15, 0, r0, c1, c0, 0\n"
@@ -156,6 +143,9 @@
 #endif
 		"orr r0, r0, r1\n"
+
+		/* Flush the TLB */
+		"mcr p15, 0, r0, c8, c7, 0\n"
 		
-		/* Store settings */
+		/* Store settings, enable the MMU */
 		"mcr p15, 0, r0, c1, c0, 0\n"
 		::: "r0", "r1"
@@ -165,4 +155,5 @@
 /** Start the MMU - initialize page table and enable paging. */
 void mmu_start() {
+	disable_paging();
 	init_boot_pt();
 	enable_paging();