Changeset 571addd in mainline for kernel/genarch
- Timestamp:
- 2010-07-27T21:42:47Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 69a60c4
- Parents:
- 5a9f4d7 (diff), 1720cf9 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - Location:
- kernel/genarch
- Files:
-
- 1 added
- 4 edited
-
Makefile.inc (modified) (1 diff)
-
include/drivers/s3c24xx_irqc/s3c24xx_irqc.h (modified) (2 diffs)
-
include/drivers/s3c24xx_uart/s3c24xx_uart.h (modified) (1 diff)
-
src/drivers/s3c24xx_irqc/s3c24xx_irqc.c (added)
-
src/drivers/s3c24xx_uart/s3c24xx_uart.c (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/genarch/Makefile.inc
r5a9f4d7 r571addd 90 90 endif 91 91 92 ifeq ($(CONFIG_S3C24XX_IRQC),y) 93 GENARCH_SOURCES += \ 94 genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c 95 endif 96 92 97 ifeq ($(CONFIG_S3C24XX_UART),y) 93 98 GENARCH_SOURCES += \ -
kernel/genarch/include/drivers/s3c24xx_irqc/s3c24xx_irqc.h
r5a9f4d7 r571addd 53 53 ioport32_t subsrcpnd; /**< Sub source pending */ 54 54 ioport32_t intsubmsk; /** Interrupt sub mask */ 55 } s3c24xx_irqc_ t;55 } s3c24xx_irqc_regs_t; 56 56 57 57 /** S3C24xx Interrupt source numbers. … … 120 120 #define S3C24XX_SUBINT_BIT(subsource) (1 << (subsource)) 121 121 122 typedef struct { 123 s3c24xx_irqc_regs_t *regs; 124 } s3c24xx_irqc_t; 125 126 extern void s3c24xx_irqc_init(s3c24xx_irqc_t *, s3c24xx_irqc_regs_t *); 127 extern unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *); 128 extern void s3c24xx_irqc_clear(s3c24xx_irqc_t *, unsigned); 129 extern void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *, unsigned); 130 extern void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *, unsigned); 131 extern void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *, unsigned); 132 extern void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *, unsigned); 133 122 134 #endif 123 135 -
kernel/genarch/include/drivers/s3c24xx_uart/s3c24xx_uart.h
r5a9f4d7 r571addd 38 38 #define KERN_S3C24XX_UART_H_ 39 39 40 #include <ddi/irq.h> 41 #include <console/chardev.h> 40 42 #include <typedefs.h> 41 #include <console/chardev.h>42 43 43 extern outdev_t *s3c24xx_uart_init(ioport8_t *); 44 /** S3C24xx UART I/O */ 45 typedef struct { 46 uint32_t ulcon; 47 uint32_t ucon; 48 uint32_t ufcon; 49 uint32_t umcon; 50 51 uint32_t utrstat; 52 uint32_t uerstat; 53 uint32_t ufstat; 54 uint32_t umstat; 55 56 uint32_t utxh; 57 uint32_t urxh; 58 59 uint32_t ubrdiv; 60 } s3c24xx_uart_io_t; 61 62 /** S3C24xx UART instance */ 63 typedef struct { 64 s3c24xx_uart_io_t *io; 65 indev_t *indev; 66 irq_t irq; 67 } s3c24xx_uart_t; 68 69 extern outdev_t *s3c24xx_uart_init(s3c24xx_uart_io_t *, inr_t inr); 70 extern void s3c24xx_uart_input_wire(s3c24xx_uart_t *, 71 indev_t *); 44 72 45 73 #endif -
kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c
r5a9f4d7 r571addd 40 40 #include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h> 41 41 #include <console/chardev.h> 42 #include <console/console.h> 43 #include <ddi/device.h> 42 44 #include <arch/asm.h> 43 45 #include <mm/slab.h> 44 #include <console/console.h>45 46 #include <sysinfo/sysinfo.h> 46 47 #include <str.h> 47 48 48 /* * S3C24xx UART register offsets*/49 #define S3C24XX_UTRSTAT 0x1050 #define S3C24XX_UT XH 0x2049 /* Bits in UTRSTAT register */ 50 #define S3C24XX_UTRSTAT_TX_EMPTY 0x4 51 #define S3C24XX_UTRSTAT_RDATA 0x1 51 52 52 /* Bits in UTXH register */ 53 #define S3C24XX_UTXH_TX_EMPTY 0x4 54 55 typedef struct { 56 ioport8_t *base; 57 } s3c24xx_uart_instance_t; 53 #define S3C24XX_UFSTAT_TX_FULL 0x4000 54 #define S3C24XX_UFSTAT_RX_FULL 0x0040 55 #define S3C24XX_UFSTAT_RX_COUNT 0x002f 58 56 59 57 static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte) 60 58 { 61 s3c24xx_uart_instance_t *instance = 62 (s3c24xx_uart_instance_t *) dev->data; 63 ioport32_t *utrstat, *utxh; 59 s3c24xx_uart_t *uart = 60 (s3c24xx_uart_t *) dev->data; 64 61 65 utrstat = (ioport32_t *) (instance->base + S3C24XX_UTRSTAT); 66 utxh = (ioport32_t *) (instance->base + S3C24XX_UTXH); 67 68 /* Wait for transmitter to be empty. */ 69 while ((pio_read_32(utrstat) & S3C24XX_UTXH_TX_EMPTY) == 0) 62 /* Wait for space becoming available in Tx FIFO. */ 63 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0) 70 64 ; 71 65 72 pio_write_32( utxh, byte);66 pio_write_32(&uart->io->utxh, byte); 73 67 } 74 68 … … 86 80 } 87 81 82 static irq_ownership_t s3c24xx_uart_claim(irq_t *irq) 83 { 84 return IRQ_ACCEPT; 85 } 86 87 static void s3c24xx_uart_irq_handler(irq_t *irq) 88 { 89 s3c24xx_uart_t *uart = irq->instance; 90 91 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) { 92 uint32_t data = pio_read_32(&uart->io->urxh); 93 pio_read_32(&uart->io->uerstat); 94 indev_push_character(uart->indev, data & 0xff); 95 } 96 } 97 88 98 static outdev_operations_t s3c24xx_uart_ops = { 89 99 .write = s3c24xx_uart_putchar, … … 91 101 }; 92 102 93 outdev_t *s3c24xx_uart_init( ioport8_t *base)103 outdev_t *s3c24xx_uart_init(s3c24xx_uart_io_t *io, inr_t inr) 94 104 { 95 105 outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC); … … 97 107 return NULL; 98 108 99 s3c24xx_uart_ instance_t *instance=100 malloc(sizeof(s3c24xx_uart_ instance_t), FRAME_ATOMIC);101 if (! instance) {109 s3c24xx_uart_t *uart = 110 malloc(sizeof(s3c24xx_uart_t), FRAME_ATOMIC); 111 if (!uart) { 102 112 free(uart_dev); 103 113 return NULL; … … 105 115 106 116 outdev_initialize("s3c24xx_uart_dev", uart_dev, &s3c24xx_uart_ops); 107 uart_dev->data = instance;117 uart_dev->data = uart; 108 118 109 instance->base = base; 119 uart->io = io; 120 uart->indev = NULL; 121 122 /* Initialize IRQ structure. */ 123 irq_initialize(&uart->irq); 124 uart->irq.devno = device_assign_devno(); 125 uart->irq.inr = inr; 126 uart->irq.claim = s3c24xx_uart_claim; 127 uart->irq.handler = s3c24xx_uart_irq_handler; 128 uart->irq.instance = uart; 129 130 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */ 131 pio_write_32(&uart->io->ufcon, 0x01); 132 133 /* Set RX interrupt to pulse mode */ 134 pio_write_32(&uart->io->ucon, 135 pio_read_32(&uart->io->ucon) & ~(1 << 8)); 110 136 111 137 if (!fb_exported) { … … 116 142 sysinfo_set_item_val("fb", NULL, true); 117 143 sysinfo_set_item_val("fb.kind", NULL, 3); 118 sysinfo_set_item_val("fb.address.physical", NULL, KA2PA( base));144 sysinfo_set_item_val("fb.address.physical", NULL, KA2PA(io)); 119 145 120 146 fb_exported = true; … … 124 150 } 125 151 152 void s3c24xx_uart_input_wire(s3c24xx_uart_t *uart, indev_t *indev) 153 { 154 ASSERT(uart); 155 ASSERT(indev); 156 157 uart->indev = indev; 158 irq_register(&uart->irq); 159 } 160 126 161 /** @} 127 162 */
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