Changeset 5626277 in mainline for arch

Timestamp:

2006-04-29T22:12:40Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

51a7dc1

Parents:

407862e

Message:

Added support for IRQ notifiactions.

• seems to work correctly on ia32, amd64
• the mips kbd probably lowers interrupts when the char is read from the port, we will have to find a way how to deal with it.

Location:

arch

Files:

• amd64/src/interrupt.c (modified) (2 diffs)
• ia32/src/interrupt.c (modified) (2 diffs)
• mips32/include/interrupt.h (modified) (1 diff)
• mips32/src/interrupt.c (modified) (4 diffs)

arch/amd64/src/interrupt.c

@@ -45 +45 @@
 #include <synch/spinlock.h>
 #include <arch/ddi/ddi.h>
+#include <interrupt.h>
+#include <ipc/sysipc.h>
 
 void print_info_errcode(int n, istate_t *istate)
@@ -154 +156 @@
 
 }
+
+static void ipc_int(int n, istate_t *istate)
+{
+        trap_virtual_eoi();
+        ipc_irq_send_notif(n-IVT_IRQBASE);
+}
+
+
+/* Reregister irq to be IPC-ready */
+void irq_ipc_bind_arch(__native irq)
+{
+        if (irq == IRQ_CLK)
+                return;
+        exc_register(IVT_IRQBASE+irq, "ipc_int", ipc_int);
+}

arch/ia32/src/interrupt.c

@@ -44 +44 @@
 #include <synch/spinlock.h>
 #include <arch/ddi/ddi.h>
+#include <ipc/sysipc.h>
+#include <interrupt.h>
 
 /*
@@ -185 +187 @@
 
 }
+
+static void ipc_int(int n, istate_t *istate)
+{
+        trap_virtual_eoi();
+        ipc_irq_send_notif(n-IVT_IRQBASE);
+}
+
+
+/* Reregister irq to be IPC-ready */
+void irq_ipc_bind_arch(__native irq)
+{
+        if (irq == IRQ_CLK)
+                return;
+        exc_register(IVT_IRQBASE+irq, "ipc_int", ipc_int);
+}

arch/mips32/include/interrupt.h

@@ -34 +34 @@
 #define IVT_ITEMS   40
 #define INT_OFFSET  32
+#define IRQ_COUNT   8
 
 #define int_register(it, name, handler) exc_register(((it)+INT_OFFSET),name,handler)

arch/mips32/src/interrupt.c

@@ -34 +34 @@
 #include <time/clock.h>
 #include <arch/drivers/arc.h>
+
+#include <ipc/sysipc.h>
 
 /** Disable interrupts.
@@ -84 +86 @@
 {
         cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
+        ipc_irq_send_notif(0);
 }
 
@@ -89 +92 @@
 {
         cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
+        ipc_irq_send_notif(1);
 }
 
@@ -98 +102 @@
         int_register(1, "swint1", swint1);
 }
+
+#include <print.h>
+static void ipc_int(int n, istate_t *istate)
+{
+        ipc_irq_send_notif(n-INT_OFFSET);
+}
+
+/* Reregister irq to be IPC-ready */
+void irq_ipc_bind_arch(__native irq)
+{
+        /* Do not allow to redefine timer */
+        /* Swint0, Swint1 are already handled */
+        if (irq == TIMER_IRQ || irq < 2)
+                return;
+        int_register(irq, "ipc_int", ipc_int);
+}