Changeset 53f9821 in mainline for arch/amd64

Timestamp:

2006-03-20T20:32:17Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

018d957e

Parents:

9d3e185

Message:

Cleanup of spinlocks, now compiles both ia32 and amd64 with
and without DEBUG_SPINLOCKS. Made spinlocks inline.
Moved syscall_handler to generic (it was identical for ia32,amd64 & mips32).
Made slightly faster syscall for ia32.
Made better interrupt routines for ia32.
Allow not saving non-scratch registers during interrupt on ia32,amd64,mips32.
Aligned interrupt handlers on ia32,amd64, this should prevent problems
with different instruction lengths.

Location:

arch/amd64

Files:

• include/atomic.h (modified) (2 diffs)
• include/syscall.h (modified) (1 diff)
• src/interrupt.c (modified) (1 diff)
• src/syscall.c (modified) (1 diff)

arch/amd64/include/atomic.h

@@ -31 +31 @@
 
 #include <arch/types.h>
+#include <arch/barrier.h>
+#include <preemption.h>
 
 typedef struct { volatile __u64 count; } atomic_t;
@@ -102 +104 @@
 
 
-extern void spinlock_arch(volatile int *val);
+/** AMD64 specific fast spinlock */
+static inline void atomic_lock_arch(atomic_t *val)
+{
+        __u64 tmp;
+
+        preemption_disable();
+        __asm__ volatile (
+                "0:;"
+#ifdef CONFIG_HT
+                "pause;" /* Pentium 4's HT love this instruction */
+#endif
+                "mov %0, %1;"
+                "testq %1, %1;"
+                "jnz 0b;"       /* Leightweight looping on locked spinlock */
+                
+                "incq %1;"      /* now use the atomic operation */
+                "xchgq %0, %1;"
+                "testq %1, %1;"
+                "jnz 0b;"
+                : "=m"(val->count),"=r"(tmp)
+                );
+        /*
+         * Prevent critical section code from bleeding out this way up.
+         */
+        CS_ENTER_BARRIER();
+}
 
 #endif

arch/amd64/include/syscall.h

@@ -32 +32 @@
 #include <arch/types.h>
 
-extern __native syscall_handler(__native a1,__native a2, __native a3, 
-                                __native a4, __native id);
 extern void syscall_setup_cpu(void);
 

arch/amd64/src/interrupt.c

@@ -55 +55 @@
         printf("ERROR_WORD=%Q\n", istate->error_word);
         printf("%%rcs=%Q, flags=%Q, %%cr0=%Q\n", istate->cs, istate->rflags,read_cr0());
-        printf("%%rax=%Q, %%rbx=%Q, %%rcx=%Q\n",istate->rax,istate->rbx,istate->rcx);
-        printf("%%rdx=%Q, %%rsi=%Q, %%rdi=%Q\n",istate->rdx,istate->rsi,istate->rdi);
-        printf("%%r8 =%Q, %%r9 =%Q, %%r10=%Q\n",istate->r8,istate->r9,istate->r10);
-        printf("%%r11=%Q, %%r12=%Q, %%r13=%Q\n",istate->r11,istate->r12,istate->r13);
-        printf("%%r14=%Q, %%r15=%Q, %%rsp=%Q\n",istate->r14,istate->r15,&istate->stack[0]);
-        printf("%%rbp=%Q\n",istate->rbp);
-/*      
-        printf("stack: %Q, %Q, %Q\n", x[5], x[6], x[7]);
-        printf("       %Q, %Q, %Q\n", x[8], x[9], x[10]);
-        printf("       %Q, %Q, %Q\n", x[11], x[12], x[13]);
-        printf("       %Q, %Q, %Q\n", x[14], x[15], x[16]);
-*/
+        printf("%%rax=%Q, %%rcx=%Q, %%rdx=%Q\n",istate->rax,istate->rcx,istate->rdx);
+        printf("%%rsi=%Q, %%rdi=%Q, %%r8 =%Q\n",istate->rsi,istate->rdi,istate->r8);
+        printf("%%r9 =%Q, %%r10 =%Q, %%r11=%Q\n",istate->r9,istate->r10,istate->r11);
+#ifdef CONFIG_DEBUG_ALLREGS     
+        printf("%%r12=%Q, %%r13=%Q, %%r14=%Q\n",istate->r12,istate->r13,istate->r14);
+        printf("%%r15=%Q, %%rbx=%Q, %%rbp=%Q\n",istate->r15,istate->rbx,&istate->rbp);
+#endif
+        printf("%%rsp=%Q\n",&istate->stack[0]);
 }
 

arch/amd64/src/syscall.c

@@ -61 +61 @@
         write_msr(AMD_MSR_SFMASK, 0x200);
 }
-
-/** Dispatch system call */
-__native syscall_handler(__native a1, __native a2, __native a3,
-                         __native a4, __native id)
-{
-        if (id < SYSCALL_END)
-                return syscall_table[id](a1,a2,a3,a4);
-        else
-                panic("Undefined syscall %d", id);
-}