Changeset 4c754f6 in mainline for kernel/genarch

Timestamp:

2013-02-11T22:55:29Z (13 years ago)

Author:

Maurizio Lombardi <m.lombardi85@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0f66886

Parents:

40762c6

Message:

Improve the dmtimer modules initialization.

Location:

kernel/genarch

Files:

• include/drivers/am335x/cm_dpll.h (modified) (1 diff)
• include/drivers/am335x/cm_dpll_regs.h (modified) (2 diffs)
• include/drivers/am335x/cm_per.h (added)
• include/drivers/am335x/cm_per_regs.h (modified) (3 diffs)
• include/drivers/am335x/ctrl_module.h (modified) (1 diff)
• include/drivers/am335x/timer.h (modified) (2 diffs)
• src/drivers/am335x/timer.c (modified) (2 diffs)

kernel/genarch/include/drivers/am335x/cm_dpll.h

@@ -37 +37 @@
 #define _KERN_AM335X_CM_DPLL_H_
 
-#include <drivers/am335x/cm_dpll_regs.h>
+#include "cm_dpll_regs.h"
+#include "timer.h"
 
 #define AM335x_CM_DPLL_BASE_ADDRESS   0x44E00500
 #define AM335x_CM_DPLL_SIZE           256
+
+static ioport32_t *am335x_cm_dpll_timer_reg_get(am335x_cm_dpll_regs_t *cm,
+    am335x_timer_id_t id)
+{
+        switch (id) {
+        default:
+                return NULL;
+        case DMTIMER2:
+                return &cm->clksel_timer2;
+        case DMTIMER3:
+                return &cm->clksel_timer3;
+        case DMTIMER4:
+                return &cm->clksel_timer4;
+        case DMTIMER5:
+                return &cm->clksel_timer5;
+        case DMTIMER6:
+                return &cm->clksel_timer6;
+        case DMTIMER7:
+                return &cm->clksel_timer7;
+        }
+}
+
+static void am335x_clock_source_select(am335x_cm_dpll_regs_t *cm,
+    am335x_timer_id_t id, am335x_clk_src_t src)
+{
+        ioport32_t *reg = am335x_cm_dpll_timer_reg_get(cm, id);
+        if (!reg)
+                return;
+
+        *reg = (*reg & ~0x03) | src;
+}
 
 #endif

kernel/genarch/include/drivers/am335x/cm_dpll_regs.h

@@ -37 +37 @@
 #define _KERN_AM335X_CM_DPLL_REGS_H_
 
-#define AM335x_CM_CLKSEL_TIMERS_CLK32KHZ    0x02
-#define AM335x_CM_CLKSEL_TIMERS_CLKMOSC     0x01
-#define AM335x_CM_CLKSEL_TIMERS_TCLKIN      0x00
+typedef enum {
+        CLK_SRC_TCLKIN = 0x00,
+        CLK_SRC_M_OSC,
+        CLK_SRC_32_KHZ
+} am335x_clk_src_t;
 
 typedef struct am335x_cm_dpll_regs {
@@ -76 +78 @@
         ioport32_t clksel_gpio0_db;
 
-
 } am335x_cm_dpll_regs_t;
 

kernel/genarch/include/drivers/am335x/cm_per_regs.h

@@ -37 +37 @@
 #define _KERN_AM335X_CM_PER_REGS_H_
 
+#include <typedefs.h>
+
 typedef struct am335x_cm_per_regs {
 
@@ -145 +147 @@
 #define AM335x_CM_PER_MMC0_CLKCTRL_IDLEST_SHIFT     16
 
-        ioport32_ elm_clkctrl;
+        ioport32_t elm_clkctrl;
 #define AM335x_CM_PER_ELM_CLKCTRL_MODULEMODE_MASK  0x3
 #define AM335x_CM_PER_ELM_CLKCTRL_MODULEMODE_SHIFT 0
@@ -406 +408 @@
         ioport32_t const pad7[2];
 
-        ioport32_t l3_clkstctrl;
-#define AM335x_CM_PER_L3_CLKSTCTRL_CLKTRCTRL_MASK     0x3
-#define AM335x_CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SHIFT    0
-#define AM335x_CM_PER_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_FLAG (1 << 4)
-#define AM335x_CM_PER_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_FLAG (1 << 5)
+        ioport32_t ocpwp_l3_clkstctrl;
+#define AM335x_CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_MASK     0x3
+#define AM335x_CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SHIFT    0
+#define AM335x_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_FLAG (1 << 4)
+#define AM335x_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_FLAG (1 << 5)
 
         ioport32_t ocpwp_clkctrl;

kernel/genarch/include/drivers/am335x/ctrl_module.h

@@ -37 +37 @@
 #define _KERN_AM335X_CTRL_MODULE_H_
 
-#include <drivers/am335x/ctrl_module_regs.h>
+#include <typedefs.h>
+#include "ctrl_module_regs.h"
 
 #define AM335x_CTRL_MODULE_BASE_ADDRESS  0x44E10000
 #define AM335x_CTRL_MODULE_SIZE          131072 /* 128 Kb */
 
-static unsigned am335x_ctrl_module_clock_freq_get(void *base)
+typedef ioport32_t am335x_ctrl_module_t;
+
+static unsigned am335x_ctrl_module_clock_freq_get(am335x_ctrl_module_t *base)
 {
-        unsigned const control_status = AM335x_CTRL_MODULE_REG_ADDR(base,
+        unsigned const control_status = *AM335x_CTRL_MODULE_REG_ADDR(base,
             CONTROL_SYSCONFIG);
         unsigned const sysboot1 = (control_status >> 22) & 0x03;
 
-        switch (sysboot) {
+        switch (sysboot1) {
         default:
         case 0:

kernel/genarch/include/drivers/am335x/timer.h

@@ -37 +37 @@
 #define _KERN_AM335X_TIMER_H_
 
-#include "timer_regs.h"
+#include <genarch/drivers/am335x/timer_regs.h>
 
 #define AM335x_DMTIMER0_BASE_ADDRESS    0x44E05000
@@ -86 +86 @@
 
 extern void am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id,
-    unsigned hz);
+    unsigned hz, unsigned srcclk_hz);
 extern void am335x_timer_intr_ack(am335x_timer_t *timer);
 extern void am335x_timer_reset(am335x_timer_t *timer);

kernel/genarch/src/drivers/am335x/timer.c

@@ -56 +56 @@
 
 void
-am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id, unsigned hz)
+am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id, unsigned hz,
+    unsigned srcclk_hz)
 {
         uintptr_t base_addr;
@@ -86 +87 @@
         regs->tclr |= AM335x_TIMER_TCLR_AR_FLAG;
 
-        /* XXX Here we assume that the timer clock source
-         * is running at 32 Khz but this is not always the
-         * case; DMTIMER[2 - 7] can use the internal system 24 Mhz
-         * clock source or an external clock also.
-         */
-        unsigned const count = 0xFFFFFFFE - 32768 / hz;
+        /* Disable the emulation mode */
+        regs->tiocp_cfg |= AM335x_TIMER_TIOCPCFG_EMUFREE_FLAG;
+
+        unsigned const count = 0xFFFFFFFE - (srcclk_hz / hz);
         regs->tcrr = count;
         regs->tldr = count;