Changeset 4bd3f45 in mainline for kernel/arch/arm32/src


Ignore:
Timestamp:
2012-09-18T13:55:55Z (13 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
1a1b05b
Parents:
f94b95b1
Message:

arm32: Consolidate control register values

Location:
kernel/arch/arm32/src
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/src/cpu/cpu.c

    rf94b95b1 r4bd3f45  
    108108       
    109109        /* Turn off tex remap */
    110         control_reg &= ~CP15_R1_TRE_BIT;
     110        control_reg &= ~CP15_R1_TEX_REMAP_EN;
    111111        /* Turn off accessed flag */
    112         control_reg &= ~(CP15_R1_AFE_BIT | CP15_R1_HA_ENABLE_BIT | CP15_R1_ALIGNMENT_ENABLE_BIT);
     112        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
     113        /* Enable unaligned access (U bit is armv6 only) */
     114        control_reg |= CP15_R1_UNALIGNED_EN;
     115        /* Disable alignment checks */
     116        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
    113117        /* Enable caching */
    114         control_reg |= CP15_R1_CACHE_ENABLE_BIT;
     118        control_reg |= CP15_R1_CACHE_EN;
    115119       
    116120        asm volatile (

  • kernel/arch/arm32/src/exception.c

    rf94b95b1 r4bd3f45  
    143143       
    144144        /* switch on the high vectors bit */
    145         control_reg |= CP15_R1_HIGH_VECTORS_BIT;
     145        control_reg |= CP15_R1_HIGH_VECTORS_EN;
    146146       
    147147        asm volatile (
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