Index: boot/arch/sparc64/Makefile.inc
===================================================================
--- boot/arch/sparc64/Makefile.inc	(revision 95b730c2989ef950189f5439eebbd7fcc3dc2dc8)
+++ boot/arch/sparc64/Makefile.inc	(revision 49093a4659920a809fa1a13c3dfad5e9587db768)
@@ -29,4 +29,12 @@
 TMP = distroot
 
+ifeq ($(CONFIG_AOUT_ISOFS_B),n)
+	SILO_PACKAGE=silo.patched.tar.gz
+endif
+
+ifeq ($(CONFIG_AOUT_ISOFS_B),y)
+	SILO_PACKAGE=silo.tar.gz
+endif
+
 build: $(BASE)/image.iso
 
@@ -40,5 +48,5 @@
 	mkdir -p $(TMP)/boot
 	mkdir -p $(TMP)/HelenOS
-	cat arch/$(ARCH)/silo/silo.tar.gz | (cd $(TMP)/boot; tar xvfz -)
+	cat arch/$(ARCH)/silo/$(SILO_PACKAGE) | (cd $(TMP)/boot; tar xvfz -)
 	cp arch/$(ARCH)/silo/README arch/$(ARCH)/silo/COPYING $(TMP)/boot
 	cat arch/$(ARCH)/silo/silo.conf | $(SILO_CONF_FILTER) >$(TMP)/boot/silo.conf
Index: boot/arch/sparc64/loader/asm.S
===================================================================
--- boot/arch/sparc64/loader/asm.S	(revision 95b730c2989ef950189f5439eebbd7fcc3dc2dc8)
+++ boot/arch/sparc64/loader/asm.S	(revision 49093a4659920a809fa1a13c3dfad5e9587db768)
@@ -106,7 +106,26 @@
 	 * 2. Invalidate I-cache.
 	 * 3. Flush instruction pipeline.
-	 */ 
-	call	icache_flush
-	membar	#StoreStore
+	 */
+
+	/*
+	 * US3 processors have a write-invalidate cache, so explicitly
+	 * invalidating it is not required. Whether to invalidate I-cache
+	 * or not is decided according to the value of the global
+	 * "subarchitecture" variable (set in the bootstrap).
+	 */
+	set subarchitecture, %g2
+	ldub [%g2], %g2
+	cmp %g2, 3
+	be 1f
+	nop
+0:
+	call icache_flush
+	nop
+1:
+	membar #StoreStore
+	
+	/*
+	 * Flush the instruction pipeline.
+	 */
 	flush	%i7
 
@@ -135,5 +154,4 @@
 	! SF Erratum #51
 	nop
-
 .global ofw
 ofw:
Index: boot/arch/sparc64/loader/main.c
===================================================================
--- boot/arch/sparc64/loader/main.c	(revision 95b730c2989ef950189f5439eebbd7fcc3dc2dc8)
+++ boot/arch/sparc64/loader/main.c	(revision 49093a4659920a809fa1a13c3dfad5e9587db768)
@@ -40,4 +40,5 @@
 
 bootinfo_t bootinfo;
+
 component_t components[COMPONENTS];
 
@@ -55,4 +56,13 @@
 	char *timestamp = "";
 #endif
+
+/** UltraSPARC subarchitecture - 1 for US, 3 for US3 */
+uint8_t subarchitecture;
+
+/**
+ * mask of the MID field inside the ICBUS_CONFIG register shifted by
+ * MID_SHIFT bits to the right
+ */
+uint16_t mid_mask;
 
 /** Print version information. */
@@ -64,4 +74,37 @@
 }
 
+/* the lowest ID (read from the VER register) of some US3 CPU model */
+#define FIRST_US3_CPU 	0x14
+
+/* the greatest ID (read from the VER register) of some US3 CPU model */
+#define LAST_US3_CPU 	0x19
+
+/* UltraSPARC IIIi processor implementation code */
+#define US_IIIi_CODE	0x15
+
+/**
+ * Sets the global variables "subarchitecture" and "mid_mask" to
+ * correct values.
+ */
+static void detect_subarchitecture(void)
+{
+	uint64_t v;
+	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
+	
+	v = (v << 16) >> 48;
+	if ((v >= FIRST_US3_CPU) && (v <= LAST_US3_CPU)) {
+		subarchitecture = SUBARCH_US3;
+		if (v == US_IIIi_CODE)
+			mid_mask = (1 << 5) - 1;
+		else
+			mid_mask = (1 << 10) - 1;
+	} else if (v < FIRST_US3_CPU) {
+		subarchitecture = SUBARCH_US;
+		mid_mask = (1 << 5) - 1;
+	} else {
+		printf("\nThis CPU is not supported by HelenOS.");
+	}
+}
+
 void bootstrap(void)
 {
@@ -73,4 +116,5 @@
 	version_print();
 	
+	detect_subarchitecture();
 	init_components(components);
 
@@ -84,5 +128,5 @@
 		halt();
 	}
-	
+
 	if (bootinfo.memmap.total == 0) {
 		printf("Error: no memory detected, halting.\n");
Index: boot/arch/sparc64/loader/main.h
===================================================================
--- boot/arch/sparc64/loader/main.h	(revision 95b730c2989ef950189f5439eebbd7fcc3dc2dc8)
+++ boot/arch/sparc64/loader/main.h	(revision 49093a4659920a809fa1a13c3dfad5e9587db768)
@@ -42,4 +42,7 @@
 #define AP_PROCESSOR	0
 
+#define SUBARCH_US	1
+#define SUBARCH_US3	3
+
 typedef struct {
 	void *addr;
Index: boot/arch/sparc64/loader/ofwarch.c
===================================================================
--- boot/arch/sparc64/loader/ofwarch.c	(revision 95b730c2989ef950189f5439eebbd7fcc3dc2dc8)
+++ boot/arch/sparc64/loader/ofwarch.c	(revision 49093a4659920a809fa1a13c3dfad5e9587db768)
@@ -41,4 +41,8 @@
 #include "asm.h"
 
+/* these tho variables will be set by the detect_subarchitecture function */
+extern uint8_t subarchitecture;
+extern uint16_t mid_mask;
+
 void write(const char *str, const int len)
 {
@@ -57,34 +61,38 @@
 }
 
-int ofw_cpu(void)
+/**
+ * Starts all CPUs represented by following siblings of the given node,
+ * except for the current CPU.
+ *
+ * @param child		The first child of the OFW tree node whose children
+ * 			represent CPUs to be woken up.
+ * @param current_mid	MID of the current CPU, the current CPU will
+ *			(of course) not be woken up.
+ * @return		Number of CPUs which have the same parent node as
+ * 			"child".
+ */
+static int wake_cpus_in_node(phandle child, uint64_t current_mid)
 {
+	int cpus;
 	char type_name[BUF_SIZE];
-
-	phandle node;
-	node = ofw_get_child_node(ofw_root);
-	if (node == 0 || node == -1) {
-		printf("Could not find any child nodes of the root node.\n");
-		return 0;
-	}
 	
-	uint64_t current_mid;
-	
-	asm volatile ("ldxa [%1] %2, %0\n"
-	    : "=r" (current_mid)
-	    : "r" (0), "i" (ASI_UPA_CONFIG));
-	current_mid >>= UPA_CONFIG_MID_SHIFT;
-	current_mid &= UPA_CONFIG_MID_MASK;
-
-	int cpus;
-	
-	for (cpus = 0; node != 0 && node != -1; node = ofw_get_peer_node(node),
-	    cpus++) {
-		if (ofw_get_property(node, "device_type", type_name,
+	for (cpus = 0; child != 0 && child != -1;
+	    child = ofw_get_peer_node(child), cpus++) {
+		if (ofw_get_property(child, "device_type", type_name,
 		    sizeof(type_name)) > 0) {
 			if (strcmp(type_name, "cpu") == 0) {
 				uint32_t mid;
 				
-				if (ofw_get_property(node, "upa-portid", &mid,
-				    sizeof(mid)) <= 0)
+				/*
+				 * "upa-portid" for US, "portid" for US-III,
+				 * "cpuid" for US-IV
+				 */
+				if (ofw_get_property(
+				    child, "upa-portid",
+				    &mid, sizeof(mid)) <= 0
+				    && ofw_get_property(child, "portid",
+				    &mid, sizeof(mid)) <= 0
+				    && ofw_get_property(child, "cpuid",
+				    &mid, sizeof(mid)) <= 0)
 					continue;
 					
@@ -94,5 +102,5 @@
 					 */
 					(void) ofw_call("SUNW,start-cpu", 3, 1,
-					    NULL, node, KERNEL_VIRTUAL_ADDRESS,
+					    NULL, child, KERNEL_VIRTUAL_ADDRESS,
 					    bootinfo.physmem_start |
 					    AP_PROCESSOR);
@@ -105,10 +113,57 @@
 }
 
+/**
+ * Finds out the current CPU's MID and wakes up all AP processors.
+ */
+int ofw_cpu(void)
+{
+	int cpus;
+	phandle node;
+	phandle subnode;
+	phandle cpus_parent;
+	phandle cmp;
+	char name[BUF_SIZE];
+
+	/* get the current CPU MID */
+	uint64_t current_mid;
+	
+	asm volatile ("ldxa [%1] %2, %0\n"
+	    : "=r" (current_mid)
+	    : "r" (0), "i" (ASI_ICBUS_CONFIG));
+	current_mid >>= ICBUS_CONFIG_MID_SHIFT;
+
+	current_mid &= mid_mask;
+
+	/* wake up CPUs */
+	
+	cpus_parent = ofw_find_device("/ssm@0,0");
+	if (cpus_parent == 0 || cpus_parent == -1) {
+		cpus_parent = ofw_find_device("/");
+	}
+
+	node = ofw_get_child_node(cpus_parent);
+	cpus = wake_cpus_in_node(node, current_mid);
+	while (node != 0 && node != -1) {
+		if (ofw_get_property(node, "name", name,
+			sizeof(name)) > 0) {
+			if (strcmp(name, "cmp") == 0) {
+				subnode = ofw_get_child_node(node);
+				cpus += wake_cpus_in_node(subnode,
+					current_mid);
+			}
+		}
+		node = ofw_get_peer_node(node);
+	}
+	
+	return cpus;
+	
+}
+
 /** Get physical memory starting address.
  *
- * @param start Pointer to variable where the physical memory starting
- * 		address will be stored.
+ * @param start		Pointer to variable where the physical memory starting
+ *			address will be stored.
  *
- * @return Non-zero on succes, zero on failure.
+ * @return		Non-zero on succes, zero on failure.
  */
 int ofw_get_physmem_start(uintptr_t *start)
Index: boot/arch/sparc64/loader/register.h
===================================================================
--- boot/arch/sparc64/loader/register.h	(revision 95b730c2989ef950189f5439eebbd7fcc3dc2dc8)
+++ boot/arch/sparc64/loader/register.h	(revision 49093a4659920a809fa1a13c3dfad5e9587db768)
@@ -34,7 +34,6 @@
 #define PSTATE_AM_BIT   8
 
-#define ASI_UPA_CONFIG          0x4a
-#define UPA_CONFIG_MID_SHIFT    17
-#define UPA_CONFIG_MID_MASK     0x1f
+#define ASI_ICBUS_CONFIG		0x4a
+#define ICBUS_CONFIG_MID_SHIFT		17
 
 #endif
