Changes in kernel/arch/amd64/src/asm.S [e98f1c3e:45f7449] in mainline

File:

• kernel/arch/amd64/src/asm.S (modified) (15 diffs)

kernel/arch/amd64/src/asm.S

@@ -27 +27 @@
  */
 
-#include <abi/asmtool.h>
 #include <arch/pm.h>
 #include <arch/mm/page.h>
-#include <arch/istate_struct.h>
-#include <arch/kseg_struct.h>
-#include <arch/cpu.h>
-#include <arch/smp/apic.h>
 
 .text
+.global interrupt_handlers
+.global syscall_entry
+.global cpuid
+.global has_cpuid
+.global read_efer_flag
+.global set_efer_flag
+.global memcpy_from_uspace
+.global memcpy_to_uspace
+.global memcpy_from_uspace_failover_address
+.global memcpy_to_uspace_failover_address
+.global early_putchar
 
 #define MEMCPY_DST   %rdi
@@ -57 +63 @@
  *
  */
-FUNCTION_BEGIN(memcpy_from_uspace)
-FUNCTION_BEGIN(memcpy_to_uspace)
+memcpy_from_uspace:
+memcpy_to_uspace:
         movq MEMCPY_DST, %rax
         
@@ -74 +80 @@
         0:
                 ret                 /* return MEMCPY_SRC, success */
-FUNCTION_END(memcpy_from_uspace)
-FUNCTION_END(memcpy_to_uspace)
-
-SYMBOL(memcpy_from_uspace_failover_address)
-SYMBOL(memcpy_to_uspace_failover_address)
+
+memcpy_from_uspace_failover_address:
+memcpy_to_uspace_failover_address:
         xorl %eax, %eax         /* return 0, failure */
         ret
@@ -87 +91 @@
 *
 */
-FUNCTION_BEGIN(has_cpuid)
+has_cpuid:
         /* Load RFLAGS */
         pushfq
@@ -94 +98 @@
         
         /* Flip the ID bit */
-        xorl $RFLAGS_ID, %edx
+        btcl $21, %edx
         
         /* Store RFLAGS */
@@ -103 +107 @@
         /* Get the ID bit again */
         popq %rdx
-        andl $RFLAGS_ID, %eax
-        andl $RFLAGS_ID, %edx
+        andl $(1 << 21), %eax
+        andl $(1 << 21), %edx
         
         /* 0 if not supported, 1 if supported */
         xorl %edx, %eax
         ret
-FUNCTION_END(has_cpuid)
-
-FUNCTION_BEGIN(cpuid)
+
+cpuid:
         /* Preserve %rbx across function calls */
         movq %rbx, %r10
@@ -126 +129 @@
         movq %r10, %rbx
         ret
-FUNCTION_END(cpuid)
-
-/** Enable local APIC
- *
- * Enable local APIC in MSR.
- *
- */
-FUNCTION_BEGIN(enable_l_apic_in_msr)
-        movl $AMD_MSR_APIC_BASE, %ecx
+
+set_efer_flag:
+        movl $0xc0000080, %ecx
         rdmsr
-        orl $(L_APIC_BASE | AMD_APIC_BASE_GE), %eax
+        btsl %edi, %eax
         wrmsr
         ret
-FUNCTION_END(enable_l_apic_in_msr)
+
+read_efer_flag:
+        movl $0xc0000080, %ecx
+        rdmsr
+        ret
+
+#define ISTATE_OFFSET_RAX               0
+#define ISTATE_OFFSET_RBX               8
+#define ISTATE_OFFSET_RCX               16
+#define ISTATE_OFFSET_RDX               24
+#define ISTATE_OFFSET_RSI               32
+#define ISTATE_OFFSET_RDI               40
+#define ISTATE_OFFSET_RBP               48
+#define ISTATE_OFFSET_R8                56
+#define ISTATE_OFFSET_R9                64
+#define ISTATE_OFFSET_R10               72
+#define ISTATE_OFFSET_R11               80
+#define ISTATE_OFFSET_R12               88      
+#define ISTATE_OFFSET_R13               96
+#define ISTATE_OFFSET_R14               104
+#define ISTATE_OFFSET_R15               112
+#define ISTATE_OFFSET_ALIGNMENT         120
+#define ISTATE_OFFSET_RBP_FRAME         128
+#define ISTATE_OFFSET_RIP_FRAME         136
+#define ISTATE_OFFSET_ERROR_WORD        144
+#define ISTATE_OFFSET_RIP               152
+#define ISTATE_OFFSET_CS                160
+#define ISTATE_OFFSET_RFLAGS            168
+#define ISTATE_OFFSET_RSP               176
+#define ISTATE_OFFSET_SS                184
 
 /*
@@ -145 +171 @@
  * error word.
  */
-#define ISTATE_SOFT_SIZE        ISTATE_SIZE - (6 * 8)
+#define ISTATE_SOFT_SIZE        144
 
 /**
@@ -155 +181 @@
 
 .macro handler i
-SYMBOL(int_\i)
+.global int_\i
+int_\i:
 
         /*
@@ -201 +228 @@
 
         /*
-         * Is this trap from the kernel?
-         */
-        cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp)
-        jz 0f
-
-        /*
-         * Switch to kernel FS base.
-         */
-        swapgs
-        movl $AMD_MSR_FS, %ecx
-        movl %gs:KSEG_OFFSET_FSBASE, %eax
-        movl %gs:KSEG_OFFSET_FSBASE+4, %edx
-        wrmsr
-        swapgs
-
-        /*
          * Imitate a regular stack frame linkage.
          * Stop stack traces here if we came from userspace.
          */
-0:      movl $0x0, %edx
+        xorl %edx, %edx
+        cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp)
         cmovnzq %rdx, %rbp
 
@@ -261 +273 @@
         53,54,55,56,57,58,59,60,61,62,63
 
-SYMBOL(interrupt_handlers)
+interrupt_handlers:
 .irp cnt, LIST_0_63
         handler \cnt 
@@ -285 +297 @@
  *
  */
-SYMBOL(syscall_entry)
+syscall_entry:
         /* Switch to hidden %gs */
         swapgs
         
-        movq %rsp, %gs:KSEG_OFFSET_USTACK_RSP  /* save this thread's user RSP */
-        movq %gs:KSEG_OFFSET_KSTACK_RSP, %rsp  /* set this thread's kernel RSP */
-
+        /*
+         * %gs:0 Scratch space for this thread's user RSP
+         * %gs:8 Address to be used as this thread's kernel RSP
+         */
+        
+        movq %rsp, %gs:0  /* save this thread's user RSP */
+        movq %gs:8, %rsp  /* set this thread's kernel RSP */
+        
         /*
          * Note that the space needed for the imitated istate structure has been
@@ -320 +337 @@
 
         /*
-         * Switch to kernel FS base.
-         */
-        movl $AMD_MSR_FS, %ecx
-        movl %gs:KSEG_OFFSET_FSBASE, %eax
-        movl %gs:KSEG_OFFSET_FSBASE+4, %edx
-        wrmsr
-        movq ISTATE_OFFSET_RDX(%rsp), %rdx      /* restore 3rd argument */
-
-        /*
          * Save the return address and the userspace stack on locations that
          * would normally be taken by them.
          */
-        movq %gs:KSEG_OFFSET_USTACK_RSP, %rax
+        movq %gs:0, %rax
         movq %rax, ISTATE_OFFSET_RSP(%rsp)
         movq %rcx, ISTATE_OFFSET_RIP(%rsp)
@@ -412 +420 @@
  *
  */
-FUNCTION_BEGIN(early_putchar)
+early_putchar:
+        
 #if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB)))
         
@@ -540 +549 @@
         
         ret
-FUNCTION_END(early_putchar)
+