Index: uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.c =================================================================== --- uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.c (revision d1ca752d5c656d91dfd911ecbdb19339e2a047b8) +++ uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.c (revision 45f4f19577155efbab658848098dce36a9ec2b91) @@ -58,5 +58,5 @@ /* Mark as dead, used for dummy EDs at the beginning of * endpoint lists. */ - OHCI_WR(instance->status, ED_STATUS_K_FLAG); + OHCI_MEM32_WR(instance->status, ED_STATUS_K_FLAG); return; } @@ -65,5 +65,5 @@ /* Status: address, endpoint nr, direction mask and max packet size. */ - OHCI_WR(instance->status, + OHCI_MEM32_WR(instance->status, ((ep->address & ED_STATUS_FA_MASK) << ED_STATUS_FA_SHIFT) | ((ep->endpoint & ED_STATUS_EN_MASK) << ED_STATUS_EN_SHIFT) @@ -74,18 +74,18 @@ /* Low speed flag */ if (ep->speed == USB_SPEED_LOW) - OHCI_SET(instance->status, ED_STATUS_S_FLAG); + OHCI_MEM32_SET(instance->status, ED_STATUS_S_FLAG); /* Isochronous format flag */ if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS) - OHCI_SET(instance->status, ED_STATUS_F_FLAG); + OHCI_MEM32_SET(instance->status, ED_STATUS_F_FLAG); /* Set TD to the list */ const uintptr_t pa = addr_to_phys(td); - OHCI_WR(instance->td_head, pa & ED_TDHEAD_PTR_MASK); - OHCI_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK); + OHCI_MEM32_WR(instance->td_head, pa & ED_TDHEAD_PTR_MASK); + OHCI_MEM32_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK); /* Set toggle bit */ if (ep->toggle) - OHCI_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); + OHCI_MEM32_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); } Index: uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.h =================================================================== --- uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.h (revision d1ca752d5c656d91dfd911ecbdb19339e2a047b8) +++ uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.h (revision 45f4f19577155efbab658848098dce36a9ec2b91) @@ -40,9 +40,9 @@ #include -#include "../ohci_regs.h" #include "../utils/malloc32.h" #include "transfer_descriptor.h" #include "completion_codes.h" +#include "mem_access.h" /** @@ -117,6 +117,6 @@ { assert(instance); - return (OHCI_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG) - || (OHCI_RD(instance->status) & ED_STATUS_K_FLAG); + return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG) + || (OHCI_MEM32_RD(instance->status) & ED_STATUS_K_FLAG); } @@ -124,5 +124,5 @@ { assert(instance); - OHCI_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG); + OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG); } @@ -135,6 +135,6 @@ { assert(instance); - return (OHCI_RD(instance->td_head) & ED_TDHEAD_PTR_MASK) - != (OHCI_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK); + return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK) + != (OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK); } @@ -148,5 +148,5 @@ assert(instance); const uintptr_t pa = addr_to_phys(td); - OHCI_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK); + OHCI_MEM32_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK); } @@ -154,5 +154,5 @@ { assert(instance); - return OHCI_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK; + return OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK; } @@ -160,5 +160,5 @@ { assert(instance); - return OHCI_RD(instance->td_head) & ED_TDHEAD_PTR_MASK; + return OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK; } @@ -174,5 +174,5 @@ const uint32_t pa = addr_to_phys(next); assert((pa & ED_NEXT_PTR_MASK) << ED_NEXT_PTR_SHIFT == pa); - OHCI_WR(instance->next, pa); + OHCI_MEM32_WR(instance->next, pa); } @@ -180,5 +180,5 @@ { assert(instance); - return OHCI_RD(instance->next) & ED_NEXT_PTR_MASK; + return OHCI_MEM32_RD(instance->next) & ED_NEXT_PTR_MASK; } @@ -191,5 +191,5 @@ { assert(instance); - return (OHCI_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0; + return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0; } @@ -203,9 +203,9 @@ assert(instance); if (toggle) { - OHCI_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); + OHCI_MEM32_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); } else { /* Clear halted flag when reseting toggle TODO: Why? */ - OHCI_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); - OHCI_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG); + OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); + OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG); } } Index: uspace/drv/bus/usb/ohci/hw_struct/mem_access.h =================================================================== --- uspace/drv/bus/usb/ohci/hw_struct/mem_access.h (revision 45f4f19577155efbab658848098dce36a9ec2b91) +++ uspace/drv/bus/usb/ohci/hw_struct/mem_access.h (revision 45f4f19577155efbab658848098dce36a9ec2b91) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup drvusbohci + * @{ + */ +/** @file + * @brief OHCI driver + */ +#ifndef DRV_OHCI_HW_MEM_ACCESS_H +#define DRV_OHCI_HW_MEM_ACCESS_H + +#include + +#define OHCI_MEM32_WR(reg, val) reg = host2uint32_t_le(val) +#define OHCI_MEM32_RD(reg) uint32_t_le2host(reg) +#define OHCI_MEM32_SET(reg, val) reg |= host2uint32_t_le(val) +#define OHCI_MEM32_CLR(reg, val) reg &= host2uint32_t_le(~val) + +#endif + +/* + * @} + */ + Index: uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.c =================================================================== --- uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.c (revision d1ca752d5c656d91dfd911ecbdb19339e2a047b8) +++ uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.c (revision 45f4f19577155efbab658848098dce36a9ec2b91) @@ -60,5 +60,5 @@ bzero(instance, sizeof(td_t)); /* Set PID and Error code */ - OHCI_WR(instance->status, + OHCI_MEM32_WR(instance->status, ((dir[direction] & TD_STATUS_DP_MASK) << TD_STATUS_DP_SHIFT) | ((CC_NOACCESS2 & TD_STATUS_CC_MASK) << TD_STATUS_CC_SHIFT)); @@ -66,20 +66,20 @@ if (toggle == 0 || toggle == 1) { /* Set explicit toggle bit */ - OHCI_SET(instance->status, TD_STATUS_T_USE_TD_FLAG); - OHCI_SET(instance->status, toggle ? TD_STATUS_T_FLAG : 0); + OHCI_MEM32_SET(instance->status, TD_STATUS_T_USE_TD_FLAG); + OHCI_MEM32_SET(instance->status, toggle ? TD_STATUS_T_FLAG : 0); } /* Alow less data on input. */ if (dir == USB_DIRECTION_IN) { - OHCI_SET(instance->status, TD_STATUS_ROUND_FLAG); + OHCI_MEM32_SET(instance->status, TD_STATUS_ROUND_FLAG); } if (buffer != NULL) { assert(size != 0); - OHCI_WR(instance->cbp, addr_to_phys(buffer)); - OHCI_WR(instance->be, addr_to_phys(buffer + size - 1)); + OHCI_MEM32_WR(instance->cbp, addr_to_phys(buffer)); + OHCI_MEM32_WR(instance->be, addr_to_phys(buffer + size - 1)); } - OHCI_WR(instance->next, addr_to_phys(next) & TD_NEXT_PTR_MASK); + OHCI_MEM32_WR(instance->next, addr_to_phys(next) & TD_NEXT_PTR_MASK); } Index: uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.h =================================================================== --- uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.h (revision d1ca752d5c656d91dfd911ecbdb19339e2a047b8) +++ uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.h (revision 45f4f19577155efbab658848098dce36a9ec2b91) @@ -38,5 +38,5 @@ #include -#include "../ohci_regs.h" +#include "mem_access.h" #include "completion_codes.h" @@ -100,5 +100,5 @@ { assert(instance); - const int cc =(OHCI_RD(instance->status) + const int cc =(OHCI_MEM32_RD(instance->status) >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK; /* This value is changed on transfer completion, @@ -119,5 +119,5 @@ { assert(instance); - const int cc = (OHCI_RD(instance->status) + const int cc = (OHCI_MEM32_RD(instance->status) >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK; return cc_to_rc(cc); @@ -136,5 +136,5 @@ return 0; /* Buffer end points to the last byte of transfer buffer, so add 1 */ - return OHCI_RD(instance->be) - OHCI_RD(instance->cbp) + 1; + return OHCI_MEM32_RD(instance->be) - OHCI_MEM32_RD(instance->cbp) + 1; } #endif