Changeset 4512d7e in mainline for arch/mips32/src
- Timestamp:
- 2006-01-19T22:17:47Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6461d67c
- Parents:
- 64c44e8
- Location:
- arch/mips32/src/mm
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/mips32/src/mm/as.c
r64c44e8 r4512d7e 36 36 /** Install address space. 37 37 * 38 * Install ASID and if necessary, purge TLB.38 * Install ASID. 39 39 * 40 40 * @param as Address space structure. … … 44 44 entry_hi_t hi; 45 45 ipl_t ipl; 46 47 /*48 * If necessary, purge TLB.49 */50 tlb_invalidate_asid(as->asid); /* TODO: do it only if necessary */51 46 52 47 /* -
arch/mips32/src/mm/asid.c
r64c44e8 r4512d7e 29 29 30 30 #include <arch/mm/asid.h> 31 #include <synch/spinlock.h>32 #include <arch.h>33 #include <debug.h>34 31 #include <typedefs.h> 35 32 36 SPINLOCK_INITIALIZE(asid_usage_lock);37 static count_t asid_usage[ASIDS]; /**< Usage tracking array for ASIDs */38 39 /** Get ASID40 *41 * Get the least used ASID.42 *43 * @return ASID44 */45 asid_t asid_get(void)46 {47 ipl_t ipl;48 int i, j;49 count_t min;50 51 min = (unsigned) -1;52 53 ipl = interrupts_disable();54 spinlock_lock(&asid_usage_lock);55 56 for (i = ASID_START, j = ASID_START; i < ASIDS; i++) {57 if (asid_usage[i] < min) {58 j = i;59 min = asid_usage[i];60 if (!min)61 break;62 }63 }64 65 asid_usage[j]++;66 67 spinlock_unlock(&asid_usage_lock);68 interrupts_restore(ipl);69 70 return i;71 }72 73 /** Release ASID74 *75 * Release ASID by decrementing its usage count.76 *77 * @param asid ASID.78 */79 void asid_put(asid_t asid)80 {81 ipl_t ipl;82 83 ipl = interrupts_disable();84 spinlock_lock(&asid_usage_lock);85 86 ASSERT(asid != ASID_INVALID);87 88 ASSERT(asid_usage[asid] > 0);89 asid_usage[asid]--;90 91 spinlock_unlock(&asid_usage_lock);92 interrupts_restore(ipl);93 }94 95 /** Find out whether ASID is used by more address spaces96 *97 * Find out whether ASID is used by more address spaces.98 *99 * @param asid ASID in question.100 *101 * @return True if 'asid' is used by more address spaces, false otherwise.102 */103 bool asid_has_conflicts(asid_t asid)104 {105 bool has_conflicts = false;106 ipl_t ipl;107 108 ASSERT(asid != ASID_INVALID);109 110 ipl = interrupts_disable();111 spinlock_lock(&asid_usage_lock);112 113 if (asid_usage[asid] > 1)114 has_conflicts = true;115 116 spinlock_unlock(&asid_usage_lock);117 interrupts_restore(ipl);118 119 return has_conflicts;120 } -
arch/mips32/src/mm/tlb.c
r64c44e8 r4512d7e 28 28 29 29 #include <arch/mm/tlb.h> 30 #include < arch/mm/asid.h>30 #include <mm/asid.h> 31 31 #include <mm/tlb.h> 32 32 #include <mm/page.h> … … 495 495 } 496 496 497 /** Invalidate TLB entr y for specified page belonging to specified address space.497 /** Invalidate TLB entries for specified page range belonging to specified address space. 498 498 * 499 499 * @param asid Address space identifier. 500 * @param page Page whose TLB entry is to be invalidated. 501 */ 502 void tlb_invalidate_page(asid_t asid, __address page) 503 { 500 * @param page First page whose TLB entry is to be invalidated. 501 * @param cnt Number of entries to invalidate. 502 */ 503 void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) 504 { 505 int i; 504 506 ipl_t ipl; 505 507 entry_lo_t lo0, lo1; … … 512 514 ipl = interrupts_disable(); 513 515 514 hi.value = 0; 515 prepare_entry_hi(&hi, asid, page); 516 cp0_entry_hi_write(hi.value); 517 518 tlbp(); 519 index.value = cp0_index_read(); 520 521 if (!index.p) { 522 /* Entry was found, index register contains valid index. */ 523 tlbr(); 524 525 lo0.value = cp0_entry_lo0_read(); 526 lo1.value = cp0_entry_lo1_read(); 527 528 lo0.v = 0; 529 lo1.v = 0; 530 531 cp0_entry_lo0_write(lo0.value); 532 cp0_entry_lo1_write(lo1.value); 533 534 tlbwi(); 516 for (i = 0; i < cnt; i++) { 517 hi.value = 0; 518 prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); 519 cp0_entry_hi_write(hi.value); 520 521 tlbp(); 522 index.value = cp0_index_read(); 523 524 if (!index.p) { 525 /* Entry was found, index register contains valid index. */ 526 tlbr(); 527 528 lo0.value = cp0_entry_lo0_read(); 529 lo1.value = cp0_entry_lo1_read(); 530 531 lo0.v = 0; 532 lo1.v = 0; 533 534 cp0_entry_lo0_write(lo0.value); 535 cp0_entry_lo1_write(lo1.value); 536 537 tlbwi(); 538 } 535 539 } 536 540
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