Changes in kernel/arch/sparc64/src/asm.S [18baf9c0:44539b4c] in mainline

File:

• kernel/arch/sparc64/src/asm.S (modified) (2 diffs)

kernel/arch/sparc64/src/asm.S

@@ -29 +29 @@
 #include <arch/arch.h>
 #include <arch/stack.h>
+#include <arch/regdef.h>
+#include <arch/mm/mmu.h>
 
 .text
@@ -232 +234 @@
         nop
 
+
+.macro WRITE_ALTERNATE_REGISTER reg, bit
+        rdpr %pstate, %g1                               ! save PSTATE.PEF
+        wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
+        mov %o0, \reg
+        wrpr %g0, PSTATE_PRIV_BIT, %pstate
+        retl
+        wrpr %g1, 0, %pstate                            ! restore PSTATE.PEF
+.endm
+
+.macro READ_ALTERNATE_REGISTER reg, bit
+        rdpr %pstate, %g1                               ! save PSTATE.PEF
+        wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
+        mov \reg, %o0
+        wrpr %g0, PSTATE_PRIV_BIT, %pstate
+        retl
+        wrpr %g1, 0, %pstate                            ! restore PSTATE.PEF
+.endm
+
+.global write_to_ag_g6
+write_to_ag_g6:
+        WRITE_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT
+
+.global write_to_ag_g7
+write_to_ag_g7:
+        WRITE_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT
+
+.global write_to_ig_g6
+write_to_ig_g6:
+        WRITE_ALTERNATE_REGISTER %g6, PSTATE_IG_BIT
+
+.global read_from_ag_g7
+read_from_ag_g7:
+        READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT
+
+
+/** Switch to userspace.
+ *
+ * %o0  Userspace entry address.
+ * %o1  Userspace stack pointer address.
+ * %o2  Userspace address of uarg structure.
+ */
+.global switch_to_userspace
+switch_to_userspace:
+        save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
+        flushw
+        wrpr %g0, 0, %cleanwin          ! avoid information leak
+
+        mov %i2, %o0                    ! uarg
+        xor %o1, %o1, %o1               ! %o1 is defined to hold pcb_ptr
+                                        ! set it to 0
+
+        clr %i2
+        clr %i3
+        clr %i4
+        clr %i5
+        clr %i6
+
+        wrpr %g0, 1, %tl                ! enforce mapping via nucleus
+
+        rdpr %cwp, %g1
+        wrpr %g1, TSTATE_IE_BIT, %tstate
+        wrpr %i0, 0, %tnpc
+        
+        /*
+         * Set primary context according to secondary context.
+         * Secondary context has been already installed by
+         * higher-level functions.
+         */
+        wr %g0, ASI_DMMU, %asi
+        ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1
+        stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi
+        flush %i7
+
+        /*
+         * Spills and fills will be handled by the userspace handlers.
+         */
+        wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate
+        
+        done                            ! jump to userspace
+