Changeset 3c79afe in mainline for kernel/genarch/src
- Timestamp:
- 2009-03-12T17:54:24Z (16 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3a1c048
- Parents:
- a0e1b48
- Location:
- kernel/genarch/src/drivers
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/genarch/src/drivers/i8042/i8042.c
ra0e1b48 r3c79afe 27 27 */ 28 28 29 /** @addtogroup genarch 29 /** @addtogroup genarch 30 30 * @{ 31 31 */ 32 32 /** 33 33 * @file 34 * @brief 34 * @brief i8042 processor driver 35 35 * 36 36 * It takes care of the i8042 serial communication. … … 43 43 #include <mm/slab.h> 44 44 45 #define i8042_SET_COMMAND 0x60 46 #define i8042_COMMAND 0x69 45 indev_operations_t kbrdin_ops = { 46 .poll = NULL 47 }; 47 48 48 #define i8042_BUFFER_FULL_MASK 0x01 49 #define i8042_WAIT_MASK 0x02 49 #define i8042_SET_COMMAND 0x60 50 #define i8042_COMMAND 0x69 51 52 #define i8042_BUFFER_FULL_MASK 0x01 53 #define i8042_WAIT_MASK 0x02 50 54 51 55 static irq_ownership_t i8042_claim(irq_t *irq) … … 53 57 i8042_instance_t *i8042_instance = irq->instance; 54 58 i8042_t *dev = i8042_instance->i8042; 59 55 60 if (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK) 56 61 return IRQ_ACCEPT; … … 63 68 i8042_instance_t *instance = irq->instance; 64 69 i8042_t *dev = instance->i8042; 65 66 uint8_t data;67 70 uint8_t status; 68 71 69 72 if (((status = pio_read_8(&dev->status)) & i8042_BUFFER_FULL_MASK)) { 70 data = pio_read_8(&dev->data); 71 72 if (instance->devout) 73 chardev_push_character(instance->devout, data); 73 uint8_t data = pio_read_8(&dev->data); 74 indev_push_character(&instance->kbrdin, data); 74 75 } 75 76 } 76 77 77 78 /** Initialize i8042. */ 78 bool 79 i8042_init(i8042_t *dev, devno_t devno, inr_t inr, chardev_t *devout) 79 indev_t *i8042_init(i8042_t *dev, devno_t devno, inr_t inr) 80 80 { 81 i8042_instance_t *instance; 82 83 instance = malloc(sizeof(i8042_instance_t), FRAME_ATOMIC); 81 i8042_instance_t *instance 82 = malloc(sizeof(i8042_instance_t), FRAME_ATOMIC); 84 83 if (!instance) 85 return false; 84 return NULL; 85 86 indev_initialize("i8042", &instance->kbrdin, &kbrdin_ops); 86 87 87 88 instance->devno = devno; 88 89 instance->i8042 = dev; 89 instance->devout = devout;90 90 91 91 irq_initialize(&instance->irq); … … 103 103 (void) pio_read_8(&dev->data); 104 104 105 return true;105 return &instance->kbrdin; 106 106 } 107 107 -
kernel/genarch/src/drivers/ns16550/ns16550.c
ra0e1b48 r3c79afe 27 27 */ 28 28 29 /** @addtogroup genarch 29 /** @addtogroup genarch 30 30 * @{ 31 31 */ 32 32 /** 33 33 * @file 34 * @brief 34 * @brief NS 16550 serial controller driver. 35 35 */ 36 36 … … 41 41 #include <mm/slab.h> 42 42 43 #define LSR_DATA_READY 0x01 43 #define LSR_DATA_READY 0x01 44 45 indev_operations_t kbrdin_ops = { 46 .poll = NULL 47 }; 48 49 static irq_ownership_t ns16550_claim(irq_t *irq) 50 { 51 ns16550_instance_t *instance = irq->instance; 52 ns16550_t *dev = instance->ns16550; 53 54 if (pio_read_8(&dev->lsr) & LSR_DATA_READY) 55 return IRQ_ACCEPT; 56 else 57 return IRQ_DECLINE; 58 } 59 60 static void ns16550_irq_handler(irq_t *irq) 61 { 62 ns16550_instance_t *instance = irq->instance; 63 ns16550_t *dev = instance->ns16550; 64 65 if (pio_read_8(&dev->lsr) & LSR_DATA_READY) { 66 uint8_t x = pio_read_8(&dev->rbr); 67 chardev_push_character(&instance->kbrdin, x); 68 } 69 } 44 70 45 71 /** Initialize ns16550. 46 72 * 47 * @param dev Addrress of the beginning of the device in I/O space. 48 * @param devno Device number. 49 * @param inr Interrupt number. 50 * @param cir Clear interrupt function. 51 * @param cir_arg First argument to cir. 52 * @param devout Output character device. 73 * @param dev Addrress of the beginning of the device in I/O space. 74 * @param devno Device number. 75 * @param inr Interrupt number. 76 * @param cir Clear interrupt function. 77 * @param cir_arg First argument to cir. 53 78 * 54 * @return True on success, false on failure. 79 * @return Keyboard device pointer or NULL on failure. 80 * 55 81 */ 56 bool 57 ns16550_init(ns16550_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg, 58 chardev_t *devout) 82 indev_t *ns16550_init(ns16550_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg) 59 83 { 60 ns16550_instance_t *instance; 84 ns16550_instance_t *instance 85 = malloc(sizeof(ns16550_instance_t), FRAME_ATOMIC); 86 if (!instance) 87 return NULL; 61 88 62 instance = malloc(sizeof(ns16550_instance_t), FRAME_ATOMIC); 63 if (!instance) 64 return false; 65 89 indev_initialize("ns16550", &instance->kbrdin, &kbrdin_ops); 90 66 91 instance->devno = devno; 67 92 instance->ns16550 = dev; 68 instance->devout = devout;69 93 70 94 irq_initialize(&instance->irq); … … 77 101 instance->irq.cir_arg = cir_arg; 78 102 irq_register(&instance->irq); 79 103 80 104 while ((pio_read_8(&dev->lsr) & LSR_DATA_READY)) 81 105 (void) pio_read_8(&dev->rbr); … … 85 109 pio_write_8(&dev->mcr, MCR_OUT2); 86 110 87 return true; 88 } 89 90 irq_ownership_t ns16550_claim(irq_t *irq) 91 { 92 ns16550_instance_t *instance = irq->instance; 93 ns16550_t *dev = instance->ns16550; 94 95 if (pio_read_8(&dev->lsr) & LSR_DATA_READY) 96 return IRQ_ACCEPT; 97 else 98 return IRQ_DECLINE; 99 } 100 101 void ns16550_irq_handler(irq_t *irq) 102 { 103 ns16550_instance_t *instance = irq->instance; 104 ns16550_t *dev = instance->ns16550; 105 106 if (pio_read_8(&dev->lsr) & LSR_DATA_READY) { 107 uint8_t x; 108 109 x = pio_read_8(&dev->rbr); 110 if (instance->devout) 111 chardev_push_character(instance->devout, x); 112 } 111 return &instance->kbrdin; 113 112 } 114 113 -
kernel/genarch/src/drivers/z8530/z8530.c
ra0e1b48 r3c79afe 27 27 */ 28 28 29 /** @addtogroup genarch 29 /** @addtogroup genarch 30 30 * @{ 31 31 */ 32 32 /** 33 33 * @file 34 * @brief 34 * @brief Zilog 8530 serial controller driver. 35 35 */ 36 36 … … 41 41 #include <mm/slab.h> 42 42 43 indev_operations_t kbrdin_ops = { 44 .poll = NULL 45 }; 46 43 47 static inline void z8530_write(ioport8_t *ctl, uint8_t reg, uint8_t val) 44 48 { … … 47 51 * command as their bit 3 is 1. 48 52 */ 49 pio_write_8(ctl, reg); /* select register */50 pio_write_8(ctl, val); /* write value */53 pio_write_8(ctl, reg); /* Select register */ 54 pio_write_8(ctl, val); /* Write value */ 51 55 } 52 56 … … 57 61 * command as their bit 3 is 1. 58 62 */ 59 pio_write_8(ctl, reg); /* select register */63 pio_write_8(ctl, reg); /* Select register */ 60 64 return pio_read_8(ctl); 61 65 } 62 66 67 static irq_ownership_t z8530_claim(irq_t *irq) 68 { 69 z8530_instance_t *instance = irq->instance; 70 z8530_t *dev = instance->z8530; 71 72 if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) 73 return IRQ_ACCEPT; 74 else 75 return IRQ_DECLINE; 76 } 77 78 static void z8530_irq_handler(irq_t *irq) 79 { 80 z8530_instance_t *instance = irq->instance; 81 z8530_t *dev = instance->z8530; 82 83 if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) { 84 uint8_t x = z8530_read(&dev->ctl_a, RR8); 85 chardev_push_character(&instance->kbrdin, x); 86 } 87 } 88 63 89 /** Initialize z8530. */ 64 bool 65 z8530_init(z8530_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg, 66 chardev_t *devout) 90 indev_t *z8530_init(z8530_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg) 67 91 { 68 z8530_instance_t *instance; 69 70 instance = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC); 92 z8530_instance_t *instance 93 = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC); 71 94 if (!instance) 72 95 return false; 73 96 97 indev_initialize("z8530", &instance->kbrdin, &kbrdin_ops); 98 74 99 instance->devno = devno; 75 100 instance->z8530 = dev; 76 instance->devout = devout; 77 101 78 102 irq_initialize(&instance->irq); 79 103 instance->irq.devno = devno; … … 85 109 instance->irq.cir_arg = cir_arg; 86 110 irq_register(&instance->irq); 87 111 88 112 (void) z8530_read(&dev->ctl_a, RR8); 89 113 90 114 /* 91 115 * Clear any pending TX interrupts or we never manage … … 93 117 */ 94 118 z8530_write(&dev->ctl_a, WR0, WR0_TX_IP_RST); 95 119 96 120 /* interrupt on all characters */ 97 121 z8530_write(&dev->ctl_a, WR1, WR1_IARCSC); 98 122 99 123 /* 8 bits per character and enable receiver */ 100 124 z8530_write(&dev->ctl_a, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE); … … 102 126 /* Master Interrupt Enable. */ 103 127 z8530_write(&dev->ctl_a, WR9, WR9_MIE); 104 105 return true; 106 } 107 108 irq_ownership_t z8530_claim(irq_t *irq) 109 { 110 z8530_instance_t *instance = irq->instance; 111 z8530_t *dev = instance->z8530; 112 113 if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) 114 return IRQ_ACCEPT; 115 else 116 return IRQ_DECLINE; 117 } 118 119 void z8530_irq_handler(irq_t *irq) 120 { 121 z8530_instance_t *instance = irq->instance; 122 z8530_t *dev = instance->z8530; 123 uint8_t x; 124 125 if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) { 126 x = z8530_read(&dev->ctl_a, RR8); 127 if (instance->devout) 128 chardev_push_character(instance->devout, x); 129 } 128 129 return &instance->kbrdin; 130 130 } 131 131
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