Changeset 3bacee1 in mainline for uspace/drv/fb/amdm37x_dispc
- Timestamp:
- 2018-04-12T16:27:17Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3cf22f9
- Parents:
- 76d0981d
- git-author:
- Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/fb/amdm37x_dispc/amdm37x_dispc.c
r76d0981d r3bacee1 126 126 visual_t visual = VISUAL_BGR_8_8_8; 127 127 switch (CONFIG_BFB_BPP) { 128 case 8: visual = VISUAL_INDIRECT_8; break; 129 case 16: visual = VISUAL_RGB_5_6_5_LE; break; 130 case 24: visual = VISUAL_BGR_8_8_8; break; 131 case 32: visual = VISUAL_RGB_8_8_8_0; break; 128 case 8: 129 visual = VISUAL_INDIRECT_8; 130 break; 131 case 16: 132 visual = VISUAL_RGB_5_6_5_LE; 133 break; 134 case 24: 135 visual = VISUAL_BGR_8_8_8; 136 break; 137 case 32: 138 visual = VISUAL_RGB_8_8_8_0; 139 break; 132 140 default: 133 141 return EINVAL; 134 142 } 135 143 136 errno_t ret = pio_enable((void *)AMDM37x_DISPC_BASE_ADDRESS,137 AMDM37x_DISPC_SIZE, (void **)&instance->regs);144 errno_t ret = pio_enable((void *)AMDM37x_DISPC_BASE_ADDRESS, 145 AMDM37x_DISPC_SIZE, (void **)&instance->regs); 138 146 if (ret != EOK) { 139 147 return EIO; … … 170 178 uint32_t attrib_pixel_format = 0; 171 179 uint32_t control_data_lanes = 0; 172 switch (bpp) 173 { 180 switch (bpp) { 174 181 case 32: 175 182 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX; … … 190 197 /* Prepare sizes */ 191 198 const uint32_t size_reg = 192 (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK) 193 <<AMDM37X_DISPC_SIZE_WIDTH_SHIFT) |194 (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK) 195 <<AMDM37X_DISPC_SIZE_HEIGHT_SHIFT);199 (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK) << 200 AMDM37X_DISPC_SIZE_WIDTH_SHIFT) | 201 (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK) << 202 AMDM37X_DISPC_SIZE_HEIGHT_SHIFT); 196 203 197 204 /* modes taken from u-boot, for 1024x768 */ … … 212 219 /* Setup control register */ 213 220 uint32_t control = 0 | 214 215 216 217 221 AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG | 222 (control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) | 223 AMDM37X_DISPC_CONTROL_GPOUT0_FLAG | 224 AMDM37X_DISPC_CONTROL_GPOUT1_FLAG; 218 225 regs->control = control; 219 226 220 227 /* No gamma stuff only data */ 221 uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 222 <<AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT);228 uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME << 229 AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT); 223 230 regs->config = config; 224 231 … … 272 279 const unsigned x = mode.screen_width; 273 280 const unsigned y = mode.screen_height; 274 ddf_log_note("Setting mode: %ux%ux%u\n", x, y, bpp *8);281 ddf_log_note("Setting mode: %ux%ux%u\n", x, y, bpp * 8); 275 282 const size_t size = ALIGN_UP(x * y * bpp, PAGE_SIZE); 276 283 uintptr_t pa; … … 286 293 287 294 dispc->fb_data = buffer; 288 amdm37x_dispc_setup_fb(dispc->regs, x, y, bpp * 8, (uint32_t)pa);295 amdm37x_dispc_setup_fb(dispc->regs, x, y, bpp * 8, (uint32_t)pa); 289 296 dispc->active_fb.idx = mode.index; 290 297 dispc->active_fb.width = x; … … 326 333 dispc->fb_data + FB_POS(x, y), 327 334 *pixelmap_pixel_at(map, 328 329 335 (x + x_offset) % map->width, 336 (y + y_offset) % map->height)); 330 337 } 331 338 }
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