Changeset 3bacee1 in mainline for uspace/drv/bus/usb/xhci
- Timestamp:
- 2018-04-12T16:27:17Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3cf22f9
- Parents:
- 76d0981d
- git-author:
- Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)
- Location:
- uspace/drv/bus/usb/xhci
- Files:
-
- 12 edited
-
commands.c (modified) (1 diff)
-
debug.c (modified) (2 diffs)
-
endpoint.c (modified) (6 diffs)
-
hc.c (modified) (26 diffs)
-
hw_struct/regs.h (modified) (1 diff)
-
hw_struct/trb.h (modified) (1 diff)
-
isoch.c (modified) (25 diffs)
-
rh.c (modified) (8 diffs)
-
streams.c (modified) (15 diffs)
-
test/reg-ops.c (modified) (9 diffs)
-
transfers.c (modified) (16 diffs)
-
trb_ring.c (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/commands.c
r76d0981d r3bacee1 159 159 } 160 160 161 return cmd_link 162 ? list_get_instance(cmd_link, xhci_cmd_t, _header.link)163 :NULL;161 return cmd_link ? 162 list_get_instance(cmd_link, xhci_cmd_t, _header.link) : 163 NULL; 164 164 } 165 165 -
uspace/drv/bus/usb/xhci/debug.c
r76d0981d r3bacee1 382 382 } 383 383 384 void xhci_dump_input_ctx(const xhci_hc_t * 384 void xhci_dump_input_ctx(const xhci_hc_t *hc, const struct xhci_input_ctx *ictx) 385 385 { 386 386 xhci_device_ctx_t *device_ctx = XHCI_GET_DEVICE_CTX(ictx, hc); … … 400 400 401 401 for (uint8_t dci = 1; dci <= XHCI_EP_COUNT; dci++) 402 if (XHCI_INPUT_CTRL_CTX_DROP(*ctrl_ctx, dci) 403 ||XHCI_INPUT_CTRL_CTX_ADD(*ctrl_ctx, dci)) {402 if (XHCI_INPUT_CTRL_CTX_DROP(*ctrl_ctx, dci) || 403 XHCI_INPUT_CTRL_CTX_ADD(*ctrl_ctx, dci)) { 404 404 usb_log_debug("Endpoint context DCI %u:", dci); 405 405 xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(device_ctx, hc, dci); -
uspace/drv/bus/usb/xhci/endpoint.c
r76d0981d r3bacee1 59 59 */ 60 60 static errno_t xhci_endpoint_init(xhci_endpoint_t *xhci_ep, device_t *dev, 61 61 const usb_endpoint_descriptors_t *desc) 62 62 { 63 63 errno_t rc; … … 88 88 if (dev->speed >= USB_SPEED_SUPER) { 89 89 ep->packets_per_uframe = xhci_ep->max_burst * xhci_ep->mult; 90 if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS 91 ||ep->transfer_type == USB_TRANSFER_INTERRUPT) {90 if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS || 91 ep->transfer_type == USB_TRANSFER_INTERRUPT) { 92 92 ep->max_transfer_size = ep->max_packet_size * ep->packets_per_uframe; 93 93 } … … 100 100 * others have 2-based log of it. 101 101 */ 102 if (dev->speed >= USB_SPEED_HIGH 103 ||ep->transfer_type != USB_TRANSFER_INTERRUPT) {102 if (dev->speed >= USB_SPEED_HIGH || 103 ep->transfer_type != USB_TRANSFER_INTERRUPT) { 104 104 xhci_ep->interval = 1 << (xhci_ep->interval - 1); 105 105 } … … 141 141 */ 142 142 endpoint_t *xhci_endpoint_create(device_t *dev, 143 143 const usb_endpoint_descriptors_t *desc) 144 144 { 145 145 const usb_transfer_type_t type = USB_ED_GET_TRANSFER_TYPE(desc->endpoint); 146 146 147 xhci_endpoint_t *ep = calloc(1, sizeof(xhci_endpoint_t) 148 +(type == USB_TRANSFER_ISOCHRONOUS) * sizeof(*ep->isoch));147 xhci_endpoint_t *ep = calloc(1, sizeof(xhci_endpoint_t) + 148 (type == USB_TRANSFER_ISOCHRONOUS) * sizeof(*ep->isoch)); 149 149 if (!ep) 150 150 return NULL; … … 230 230 } 231 231 232 usb_transfer_batch_t * 232 usb_transfer_batch_t *const batch = ep->active_batch; 233 233 234 234 const errno_t err = hc_stop_endpoint(xhci_ep); … … 289 289 290 290 case USB_TRANSFER_ISOCHRONOUS: 291 return in ? EP_TYPE_ISOCH_IN 292 :EP_TYPE_ISOCH_OUT;291 return in ? EP_TYPE_ISOCH_IN : 292 EP_TYPE_ISOCH_OUT; 293 293 294 294 case USB_TRANSFER_BULK: 295 return in ? EP_TYPE_BULK_IN 296 :EP_TYPE_BULK_OUT;295 return in ? EP_TYPE_BULK_IN : 296 EP_TYPE_BULK_OUT; 297 297 298 298 case USB_TRANSFER_INTERRUPT: 299 return in ? EP_TYPE_INTERRUPT_IN 300 :EP_TYPE_INTERRUPT_OUT;299 return in ? EP_TYPE_INTERRUPT_IN : 300 EP_TYPE_INTERRUPT_OUT; 301 301 } 302 302 -
uspace/drv/bus/usb/xhci/hc.c
r76d0981d r3bacee1 87 87 xhci_port_speed_t *speeds = hc->speeds; 88 88 89 for (xhci_extcap_t * ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {89 for (xhci_extcap_t * ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) { 90 90 xhci_dump_extcap(ec); 91 91 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) { … … 151 151 * mapping also for devices connected to hubs. 152 152 */ 153 if (psiv < ARRAY_SIZE(default_psiv_to_port_speed) 154 && default_psiv_to_port_speed[psiv].major == major155 && default_psiv_to_port_speed[psiv].minor == minor156 && default_psiv_to_port_speed[psiv].rx_bps == bps157 &&default_psiv_to_port_speed[psiv].tx_bps == bps) {153 if (psiv < ARRAY_SIZE(default_psiv_to_port_speed) && 154 default_psiv_to_port_speed[psiv].major == major && 155 default_psiv_to_port_speed[psiv].minor == minor && 156 default_psiv_to_port_speed[psiv].rx_bps == bps && 157 default_psiv_to_port_speed[psiv].tx_bps == bps) { 158 158 speeds[psiv] = default_psiv_to_port_speed[psiv]; 159 159 usb_log_debug("Assumed default %s speed of USB %u.", 160 160 usb_str_speed(speeds[psiv].usb_speed), major); 161 161 continue; 162 162 } … … 173 173 speeds[psiv].tx_bps = bps; 174 174 usb_log_debug("Speed %u set up for bps %" PRIu64 175 176 175 " / %" PRIu64 ".", psiv, speeds[psiv].rx_bps, 176 speeds[psiv].tx_bps); 177 177 } 178 178 } … … 384 384 code->rangecount = 1; 385 385 code->ranges[0] = (irq_pio_range_t) { 386 387 386 .base = RNGABS(hc->mmio_range), 387 .size = RNGSZ(hc->mmio_range), 388 388 }; 389 389 … … 391 391 memcpy(code->cmds, irq_commands, sizeof(irq_commands)); 392 392 393 void *intr0_iman = RNGABSPTR(hc->mmio_range) 394 + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF)395 +offsetof(xhci_rt_regs_t, ir[0]);396 void *usbsts = RNGABSPTR(hc->mmio_range) 397 + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH)398 +offsetof(xhci_op_regs_t, usbsts);393 void *intr0_iman = RNGABSPTR(hc->mmio_range) + 394 XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + 395 offsetof(xhci_rt_regs_t, ir[0]); 396 void *usbsts = RNGABSPTR(hc->mmio_range) + 397 XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) + 398 offsetof(xhci_op_regs_t, usbsts); 399 399 400 400 code->cmds[0].addr = intr0_iman; … … 425 425 for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) { 426 426 usb_log_debug("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i, 427 428 427 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS), 428 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS)); 429 429 if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) { 430 430 return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO; … … 559 559 const uint32_t usbsts = XHCI_REG_RD_FIELD(&hc->op_regs->usbsts, 32); 560 560 561 return !(usbcmd & XHCI_REG_MASK(XHCI_OP_RS)) 562 || (usbsts & XHCI_REG_MASK(XHCI_OP_HCE))563 ||(usbsts & XHCI_REG_MASK(XHCI_OP_HSE));561 return !(usbcmd & XHCI_REG_MASK(XHCI_OP_RS)) || 562 (usbsts & XHCI_REG_MASK(XHCI_OP_HCE)) || 563 (usbsts & XHCI_REG_MASK(XHCI_OP_HSE)); 564 564 } 565 565 … … 589 589 struct timeval tv; 590 590 getuptime(&tv); 591 usb_log_debug("Microframe index wrapped (@%lu.%li, %" PRIu64" total).",591 usb_log_debug("Microframe index wrapped (@%lu.%li, %" PRIu64 " total).", 592 592 tv.tv_sec, tv.tv_usec, hc->wrap_count); 593 593 hc->wrap_time = ((uint64_t) tv.tv_sec) * 1000000 + ((uint64_t) tv.tv_usec); … … 634 634 errno_t err; 635 635 xhci_trb_t trb; 636 xhci_hc_t * 636 xhci_hc_t *const hc = arg; 637 637 assert(hc); 638 638 … … 654 654 */ 655 655 static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, 656 656 xhci_interrupter_regs_t *intr) 657 657 { 658 658 errno_t err; … … 720 720 if (status) { 721 721 usb_log_error("Non-zero status after interrupt handling (%08x) " 722 722 " - missing something?", status); 723 723 } 724 724 } … … 766 766 { 767 767 return (2 * ep->base.endpoint) + 768 (ep->base.transfer_type == USB_TRANSFER_CONTROL769 ||ep->base.direction == USB_DIRECTION_IN);768 (ep->base.transfer_type == USB_TRANSFER_CONTROL || 769 ep->base.direction == USB_DIRECTION_IN); 770 770 } 771 771 772 772 void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id) 773 773 { 774 xhci_device_t * 775 xhci_hc_t * 774 xhci_device_t *const dev = xhci_ep_to_dev(ep); 775 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 776 776 const uint8_t dci = endpoint_dci(ep); 777 777 const uint32_t target = (stream_id << 16) | (dci & 0x1ff); … … 786 786 { 787 787 errno_t err; 788 xhci_hc_t * 788 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 789 789 790 790 /* Prepare memory for the context */ … … 821 821 { 822 822 errno_t err; 823 xhci_hc_t * 823 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 824 824 xhci_cmd_t cmd; 825 825 … … 846 846 static errno_t create_configure_ep_input_ctx(xhci_device_t *dev, dma_buffer_t *dma_buf) 847 847 { 848 const xhci_hc_t * 848 const xhci_hc_t *hc = bus_to_hc(dev->base.bus); 849 849 const errno_t err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc)); 850 850 if (err) … … 870 870 { 871 871 errno_t err = ENOMEM; 872 xhci_hc_t * 872 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 873 873 xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]); 874 874 … … 920 920 errno_t hc_configure_device(xhci_device_t *dev) 921 921 { 922 xhci_hc_t * 922 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 923 923 xhci_cmd_t cmd; 924 924 … … 945 945 errno_t hc_deconfigure_device(xhci_device_t *dev) 946 946 { 947 xhci_hc_t * 947 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 948 948 xhci_cmd_t cmd; 949 949 errno_t err; … … 972 972 errno_t hc_add_endpoint(xhci_endpoint_t *ep) 973 973 { 974 xhci_device_t * 974 xhci_device_t *const dev = xhci_ep_to_dev(ep); 975 975 const unsigned dci = endpoint_dci(ep); 976 976 xhci_cmd_t cmd; … … 984 984 xhci_input_ctx_t *ictx = ictx_dma_buf.virt; 985 985 986 xhci_hc_t * 986 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 987 987 XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci); 988 988 … … 1007 1007 errno_t hc_drop_endpoint(xhci_endpoint_t *ep) 1008 1008 { 1009 xhci_device_t * 1010 xhci_hc_t * 1009 xhci_device_t *const dev = xhci_ep_to_dev(ep); 1010 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 1011 1011 const unsigned dci = endpoint_dci(ep); 1012 1012 xhci_cmd_t cmd; … … 1043 1043 errno_t hc_update_endpoint(xhci_endpoint_t *ep) 1044 1044 { 1045 xhci_device_t * 1045 xhci_device_t *const dev = xhci_ep_to_dev(ep); 1046 1046 const unsigned dci = endpoint_dci(ep); 1047 1047 xhci_cmd_t cmd; 1048 1048 1049 1049 dma_buffer_t ictx_dma_buf; 1050 xhci_hc_t * 1050 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 1051 1051 1052 1052 errno_t err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc)); … … 1078 1078 errno_t hc_stop_endpoint(xhci_endpoint_t *ep) 1079 1079 { 1080 xhci_device_t * 1080 xhci_device_t *const dev = xhci_ep_to_dev(ep); 1081 1081 const unsigned dci = endpoint_dci(ep); 1082 xhci_hc_t * 1082 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 1083 1083 xhci_cmd_t cmd; 1084 1084 errno_t err; … … 1104 1104 errno_t hc_reset_endpoint(xhci_endpoint_t *ep) 1105 1105 { 1106 xhci_device_t * 1106 xhci_device_t *const dev = xhci_ep_to_dev(ep); 1107 1107 const unsigned dci = endpoint_dci(ep); 1108 xhci_hc_t * 1108 xhci_hc_t *const hc = bus_to_hc(dev->base.bus); 1109 1109 xhci_cmd_t cmd; 1110 1110 errno_t err; … … 1126 1126 errno_t hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id) 1127 1127 { 1128 xhci_device_t * 1128 xhci_device_t *const dev = xhci_ep_to_dev(ep); 1129 1129 const unsigned dci = endpoint_dci(ep); 1130 1130 uintptr_t addr; … … 1135 1135 xhci_trb_ring_reset_dequeue_state(ring, &addr); 1136 1136 1137 xhci_hc_t * 1137 xhci_hc_t *const hc = bus_to_hc(endpoint_get_bus(&ep->base)); 1138 1138 1139 1139 xhci_cmd_init(&cmd, XHCI_CMD_SET_TR_DEQUEUE_POINTER); -
uspace/drv/bus/usb/xhci/hw_struct/regs.h
r76d0981d r3bacee1 235 235 #define XHCI_CAP_CIC hccparams2, 32, FLAG, 5 236 236 237 static inline unsigned xhci_get_max_spbuf(xhci_cap_regs_t *cap_regs) { 238 return XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_HI) << 5 239 | XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_LO); 237 static inline unsigned xhci_get_max_spbuf(xhci_cap_regs_t *cap_regs) 238 { 239 return XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_HI) << 5 | 240 XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_LO); 240 241 } 241 242 -
uspace/drv/bus/usb/xhci/hw_struct/trb.h
r76d0981d r3bacee1 166 166 167 167 return chain_bit && 168 (type == XHCI_TRB_TYPE_NORMAL 169 || type == XHCI_TRB_TYPE_DATA_STAGE170 || type == XHCI_TRB_TYPE_STATUS_STAGE171 ||type == XHCI_TRB_TYPE_ISOCH);168 (type == XHCI_TRB_TYPE_NORMAL || 169 type == XHCI_TRB_TYPE_DATA_STAGE || 170 type == XHCI_TRB_TYPE_STATUS_STAGE || 171 type == XHCI_TRB_TYPE_ISOCH); 172 172 } 173 173 -
uspace/drv/bus/usb/xhci/isoch.c
r76d0981d r3bacee1 49 49 { 50 50 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 51 xhci_isoch_t * 51 xhci_isoch_t *const isoch = ep->isoch; 52 52 53 53 fibril_mutex_initialize(&isoch->guard); … … 70 70 static void isoch_reset(xhci_endpoint_t *ep) 71 71 { 72 xhci_isoch_t * 72 xhci_isoch_t *const isoch = ep->isoch; 73 73 assert(fibril_mutex_is_locked(&isoch->guard)); 74 74 … … 87 87 static void isoch_reset_no_timer(xhci_endpoint_t *ep) 88 88 { 89 xhci_isoch_t * 89 xhci_isoch_t *const isoch = ep->isoch; 90 90 assert(fibril_mutex_is_locked(&isoch->guard)); 91 91 /* … … 97 97 } 98 98 99 static void isoch_reset_timer(void *ep) { 100 xhci_isoch_t * const isoch = xhci_endpoint_get(ep)->isoch; 99 static void isoch_reset_timer(void *ep) 100 { 101 xhci_isoch_t *const isoch = xhci_endpoint_get(ep)->isoch; 101 102 fibril_mutex_lock(&isoch->guard); 102 103 isoch_reset(ep); … … 109 110 */ 110 111 #define RESET_TIMER_DELAY 100000 111 static void timer_schedule_reset(xhci_endpoint_t *ep) { 112 xhci_isoch_t * const isoch = ep->isoch; 113 const suseconds_t delay = isoch->buffer_count * ep->interval * 125 114 + RESET_TIMER_DELAY; 112 static void timer_schedule_reset(xhci_endpoint_t *ep) 113 { 114 xhci_isoch_t *const isoch = ep->isoch; 115 const suseconds_t delay = isoch->buffer_count * ep->interval * 125 + 116 RESET_TIMER_DELAY; 115 117 116 118 fibril_timer_clear_locked(isoch->reset_timer); 117 119 fibril_timer_set_locked(isoch->reset_timer, delay, 118 120 isoch_reset_timer, ep); 119 121 } 120 122 … … 122 124 { 123 125 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 124 xhci_isoch_t * 126 xhci_isoch_t *const isoch = ep->isoch; 125 127 126 128 if (isoch->feeding_timer) { … … 141 143 * Allocate isochronous buffers. Create the feeding timer. 142 144 */ 143 errno_t isoch_alloc_transfers(xhci_endpoint_t *ep) { 144 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 145 xhci_isoch_t * const isoch = ep->isoch; 145 errno_t isoch_alloc_transfers(xhci_endpoint_t *ep) 146 { 147 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 148 xhci_isoch_t *const isoch = ep->isoch; 146 149 147 150 isoch->feeding_timer = fibril_timer_create(&isoch->guard); … … 151 154 152 155 isoch->transfers = calloc(isoch->buffer_count, sizeof(xhci_isoch_transfer_t)); 153 if (!isoch->transfers)156 if (!isoch->transfers) 154 157 goto err; 155 158 … … 185 188 size_t tdpc = it->size / 1024 + ((it->size % 1024) ? 1 : 0); 186 189 size_t tbc = tdpc / ep->max_burst; 187 if (!tdpc % ep->max_burst) --tbc; 190 if (!tdpc % ep->max_burst) 191 --tbc; 188 192 size_t bsp = tdpc % ep->max_burst; 189 193 size_t tlbpc = (bsp ? bsp : ep->max_burst) - 1; … … 220 224 */ 221 225 uint64_t epoch = hc->wrap_count; 222 if (reg_mfindex < EPOCH_LOW_MFINDEX 223 &&get_system_time() - hc->wrap_time > EPOCH_DELAY) {226 if (reg_mfindex < EPOCH_LOW_MFINDEX && 227 get_system_time() - hc->wrap_time > EPOCH_DELAY) { 224 228 ++epoch; 225 229 } … … 229 233 static inline void calc_next_mfindex(xhci_endpoint_t *ep, xhci_isoch_transfer_t *it) 230 234 { 231 xhci_isoch_t * 235 xhci_isoch_t *const isoch = ep->isoch; 232 236 if (isoch->last_mf == -1U) { 233 237 const xhci_bus_t *bus = bus_to_xhci_bus(ep->base.device->bus); … … 270 274 */ 271 275 static inline void window_decide(window_decision_t *res, xhci_hc_t *hc, 272 276 uint64_t mfindex) 273 277 { 274 278 const uint64_t current_mf = get_current_microframe(hc); … … 300 304 { 301 305 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 302 xhci_isoch_t * 306 xhci_isoch_t *const isoch = ep->isoch; 303 307 assert(fibril_mutex_is_locked(&isoch->guard)); 304 308 … … 309 313 310 314 while (isoch->transfers[isoch->hw_enqueue].state == ISOCH_FILLED) { 311 xhci_isoch_transfer_t * 315 xhci_isoch_transfer_t *const it = &isoch->transfers[isoch->hw_enqueue]; 312 316 suseconds_t delay; 313 317 … … 321 325 delay = wd.offset * 125; 322 326 usb_log_debug("[isoch] delaying feeding buffer %zu for %ldus", 323 327 it - isoch->transfers, delay); 324 328 fibril_timer_set_locked(isoch->feeding_timer, delay, 325 329 isoch_feed_out_timer, ep); … … 346 350 */ 347 351 usb_log_debug("[isoch] missed feeding buffer %zu at 0x%llx by " 348 352 "%llu uframes", it - isoch->transfers, it->mfindex, wd.offset); 349 353 it->state = ISOCH_COMPLETE; 350 354 it->error = EOK; … … 370 374 static void isoch_feed_out_timer(void *ep) 371 375 { 372 xhci_isoch_t * 376 xhci_isoch_t *const isoch = xhci_endpoint_get(ep)->isoch; 373 377 fibril_mutex_lock(&isoch->guard); 374 378 isoch_feed_out(ep); … … 386 390 { 387 391 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 388 xhci_isoch_t * 392 xhci_isoch_t *const isoch = ep->isoch; 389 393 assert(fibril_mutex_is_locked(&isoch->guard)); 390 394 … … 395 399 396 400 while (isoch->transfers[isoch->enqueue].state <= ISOCH_FILLED) { 397 xhci_isoch_transfer_t * 401 xhci_isoch_transfer_t *const it = &isoch->transfers[isoch->enqueue]; 398 402 suseconds_t delay; 399 403 … … 419 423 case WINDOW_TOO_LATE: 420 424 usb_log_debug("[isoch] missed feeding buffer %zu at 0x%llx by" 421 425 "%llu uframes", it - isoch->transfers, it->mfindex, wd.offset); 422 426 /* Missed the opportunity to schedule. Schedule ASAP. */ 423 427 it->mfindex += wd.offset; … … 458 462 static void isoch_feed_in_timer(void *ep) 459 463 { 460 xhci_isoch_t * 464 xhci_isoch_t *const isoch = xhci_endpoint_get(ep)->isoch; 461 465 fibril_mutex_lock(&isoch->guard); 462 466 isoch_feed_in(ep); … … 477 481 xhci_endpoint_t *ep = xhci_endpoint_get(transfer->batch.ep); 478 482 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 479 xhci_isoch_t * 483 xhci_isoch_t *const isoch = ep->isoch; 480 484 481 485 /* This shall be already checked by endpoint */ … … 541 545 xhci_endpoint_t *ep = xhci_endpoint_get(transfer->batch.ep); 542 546 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 543 xhci_isoch_t * 547 xhci_isoch_t *const isoch = ep->isoch; 544 548 545 549 if (transfer->batch.size < ep->base.max_transfer_size) { … … 585 589 586 590 void isoch_handle_transfer_event(xhci_hc_t *hc, xhci_endpoint_t *ep, 587 588 { 589 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 590 xhci_isoch_t * 591 xhci_trb_t *trb) 592 { 593 assert(ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS); 594 xhci_isoch_t *const isoch = ep->isoch; 591 595 592 596 fibril_mutex_lock(&ep->isoch->guard); … … 632 636 } 633 637 634 xhci_isoch_transfer_t * 638 xhci_isoch_transfer_t *const it = &isoch->transfers[di]; 635 639 636 640 if (it->state == ISOCH_FED && it->interrupt_trb_phys == trb->parameter) { -
uspace/drv/bus/usb/xhci/rh.c
r76d0981d r3bacee1 54 54 /* This mask only lists registers, which imply port change. */ 55 55 static const uint32_t port_events_mask = 56 57 58 59 60 61 62 56 XHCI_REG_MASK(XHCI_PORT_CSC) | 57 XHCI_REG_MASK(XHCI_PORT_PEC) | 58 XHCI_REG_MASK(XHCI_PORT_WRC) | 59 XHCI_REG_MASK(XHCI_PORT_OCC) | 60 XHCI_REG_MASK(XHCI_PORT_PRC) | 61 XHCI_REG_MASK(XHCI_PORT_PLC) | 62 XHCI_REG_MASK(XHCI_PORT_CEC); 63 63 64 64 static const uint32_t port_reset_mask = 65 66 65 XHCI_REG_MASK(XHCI_PORT_WRC) | 66 XHCI_REG_MASK(XHCI_PORT_PRC); 67 67 68 68 typedef struct rh_port { … … 167 167 return ENOENT; 168 168 169 unsigned psiv = (status & XHCI_REG_MASK(XHCI_PORT_PS)) 170 >>XHCI_REG_SHIFT(XHCI_PORT_PS);169 unsigned psiv = (status & XHCI_REG_MASK(XHCI_PORT_PS)) >> 170 XHCI_REG_SHIFT(XHCI_PORT_PS); 171 171 const usb_speed_t speed = port->rh->hc->speeds[psiv].usb_speed; 172 172 … … 233 233 static void handle_port_change(xhci_rh_t *rh, uint8_t port_id) 234 234 { 235 rh_port_t * 235 rh_port_t *const port = &rh->ports[port_id - 1]; 236 236 237 237 uint32_t status = XHCI_REG_RD_FIELD(&port->regs->portsc, 32); … … 280 280 281 281 void xhci_rh_set_ports_protocol(xhci_rh_t *rh, 282 282 unsigned offset, unsigned count, unsigned major) 283 283 { 284 284 for (unsigned i = offset; i < offset + count; i++) … … 297 297 handle_port_change(rh, i + 1); 298 298 299 rh_port_t * 299 rh_port_t *const port = &rh->ports[i]; 300 300 301 301 /* … … 304 304 * such ports. 305 305 */ 306 if (XHCI_REG_RD(port->regs, XHCI_PORT_CCS) 307 &&port->base.state == PORT_DISABLED)306 if (XHCI_REG_RD(port->regs, XHCI_PORT_CCS) && 307 port->base.state == PORT_DISABLED) 308 308 usb_port_connected(&port->base, &rh_enumerate_device); 309 309 } … … 320 320 321 321 for (uint8_t i = 0; i < rh->max_ports; ++i) { 322 rh_port_t * 322 rh_port_t *const port = &rh->ports[i]; 323 323 usb_port_disabled(&port->base, &rh_remove_device); 324 324 usb_port_fini(&port->base); … … 328 328 static int rh_worker(void *arg) 329 329 { 330 xhci_rh_t * 330 xhci_rh_t *const rh = arg; 331 331 332 332 xhci_trb_t trb; -
uspace/drv/bus/usb/xhci/streams.c
r76d0981d r3bacee1 88 88 { 89 89 usb_log_debug("Allocating primary stream context array of size %u " 90 90 "for endpoint " XHCI_EP_FMT, count, XHCI_EP_ARGS(*xhci_ep)); 91 91 92 92 if ((dma_buffer_alloc(&xhci_ep->primary_stream_ctx_dma, 93 93 count * sizeof(xhci_stream_ctx_t)))) { 94 94 return ENOMEM; 95 95 } … … 110 110 { 111 111 usb_log_debug("Deallocating primary stream structures for " 112 112 "endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep)); 113 113 114 114 dma_buffer_free(&xhci_ep->primary_stream_ctx_dma); … … 138 138 { 139 139 usb_log_debug("Freeing stream rings and context arrays of endpoint " 140 140 XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep)); 141 141 142 142 for (size_t index = 0; index < xhci_ep->primary_stream_data_size; ++index) { … … 153 153 */ 154 154 static errno_t initialize_primary_stream(xhci_hc_t *hc, xhci_endpoint_t *xhci_ep, 155 155 unsigned index) 156 156 { 157 157 xhci_stream_ctx_t *ctx = &xhci_ep->primary_stream_ctx_array[index]; … … 206 206 */ 207 207 static errno_t initialize_secondary_streams(xhci_hc_t *hc, xhci_endpoint_t *xhci_ep, 208 208 unsigned idx, unsigned count) 209 209 { 210 210 if (count == 0) { … … 218 218 if ((count & (count - 1)) != 0 || count < 8 || count > 256) { 219 219 usb_log_error("The secondary stream array size must be a power of 2 " 220 220 "between 8 and 256."); 221 221 return EINVAL; 222 222 } … … 233 233 234 234 if ((dma_buffer_alloc(&data->secondary_stream_ctx_dma, 235 235 count * sizeof(xhci_stream_ctx_t)))) { 236 236 free(data->secondary_data); 237 237 return ENOMEM; … … 275 275 */ 276 276 static void setup_stream_context(xhci_endpoint_t *xhci_ep, xhci_ep_ctx_t *ctx, 277 277 unsigned pstreams, unsigned lsa) 278 278 { 279 279 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(xhci_ep)); … … 295 295 */ 296 296 static errno_t verify_stream_conditions(xhci_hc_t *hc, xhci_device_t *dev, 297 298 { 299 if (xhci_ep->base.transfer_type != USB_TRANSFER_BULK 300 ||dev->base.speed != USB_SPEED_SUPER) {297 xhci_endpoint_t *xhci_ep, unsigned count) 298 { 299 if (xhci_ep->base.transfer_type != USB_TRANSFER_BULK || 300 dev->base.speed != USB_SPEED_SUPER) { 301 301 usb_log_error("Streams are only supported by superspeed bulk endpoints."); 302 302 return EINVAL; … … 321 321 if (count > max_psa_size) { 322 322 usb_log_error("Host controller only supports " 323 323 "%u primary streams.", max_psa_size); 324 324 return EINVAL; 325 325 } … … 327 327 if (count > xhci_ep->max_streams) { 328 328 usb_log_error("Endpoint " XHCI_EP_FMT " supports only %" PRIu32 " streams.", 329 329 XHCI_EP_ARGS(*xhci_ep), xhci_ep->max_streams); 330 330 return EINVAL; 331 331 } … … 346 346 */ 347 347 errno_t xhci_endpoint_remove_streams(xhci_hc_t *hc, xhci_device_t *dev, 348 348 xhci_endpoint_t *xhci_ep) 349 349 { 350 350 if (!xhci_ep->primary_stream_data_size) { … … 374 374 */ 375 375 errno_t xhci_endpoint_request_primary_streams(xhci_hc_t *hc, xhci_device_t *dev, 376 376 xhci_endpoint_t *xhci_ep, unsigned count) 377 377 { 378 378 errno_t err = verify_stream_conditions(hc, dev, xhci_ep, count); … … 422 422 */ 423 423 errno_t xhci_endpoint_request_secondary_streams(xhci_hc_t *hc, xhci_device_t *dev, 424 424 xhci_endpoint_t *xhci_ep, unsigned *sizes, unsigned count) 425 425 { 426 426 /* Check if HC supports secondary indexing */ … … 454 454 if (max * count > xhci_ep->max_streams) { 455 455 usb_log_error("Endpoint " XHCI_EP_FMT " supports only %" PRIu32 " streams.", 456 456 XHCI_EP_ARGS(*xhci_ep), xhci_ep->max_streams); 457 457 return EINVAL; 458 458 } -
uspace/drv/bus/usb/xhci/test/reg-ops.c
r76d0981d r3bacee1 23 23 #define EQ(exp, act) PCUT_ASSERT_INT_EQUALS((exp), (act)) 24 24 25 PCUT_TEST(ops_8_field) { 25 PCUT_TEST(ops_8_field) 26 { 26 27 RESET; 27 28 EQ(0, XHCI_REG_RD(regs, REG_8_FIELD)); … … 41 42 } 42 43 43 PCUT_TEST(ops_8_range) { 44 PCUT_TEST(ops_8_range) 45 { 44 46 RESET; 45 47 EQ(0, XHCI_REG_RD(regs, REG_8_RANGE)); … … 58 60 } 59 61 60 PCUT_TEST(ops_8_flag) { 62 PCUT_TEST(ops_8_flag) 63 { 61 64 RESET; 62 65 EQ(0, XHCI_REG_RD(regs, REG_8_FLAG)); … … 76 79 } 77 80 78 PCUT_TEST(ops_16_field) { 81 PCUT_TEST(ops_16_field) 82 { 79 83 RESET; 80 84 EQ(0, XHCI_REG_RD(regs, REG_16_FIELD)); … … 93 97 } 94 98 95 PCUT_TEST(ops_16_range) { 99 PCUT_TEST(ops_16_range) 100 { 96 101 RESET; 97 102 EQ(0, XHCI_REG_RD(regs, REG_16_RANGE)); … … 110 115 } 111 116 112 PCUT_TEST(ops_16_flag) { 117 PCUT_TEST(ops_16_flag) 118 { 113 119 RESET; 114 120 EQ(0, XHCI_REG_RD(regs, REG_16_FLAG)); … … 128 134 } 129 135 130 PCUT_TEST(ops_32_field) { 136 PCUT_TEST(ops_32_field) 137 { 131 138 RESET; 132 139 EQ(0, XHCI_REG_RD(regs, REG_32_FIELD)); … … 145 152 } 146 153 147 PCUT_TEST(ops_32_range) { 154 PCUT_TEST(ops_32_range) 155 { 148 156 RESET; 149 157 EQ(0, XHCI_REG_RD(regs, REG_32_RANGE)); … … 162 170 } 163 171 164 PCUT_TEST(ops_32_flag) { 172 PCUT_TEST(ops_32_flag) 173 { 165 174 RESET; 166 175 EQ(0, XHCI_REG_RD(regs, REG_32_FLAG)); -
uspace/drv/bus/usb/xhci/transfers.c
r76d0981d r3bacee1 51 51 * See Table 7 of xHCI specification. 52 52 */ 53 static inline stage_dir_flag_t get_status_direction_flag(xhci_trb_t *trb,54 53 static inline stage_dir_flag_t get_status_direction_flag(xhci_trb_t *trb, 54 uint8_t bmRequestType, uint16_t wLength) 55 55 { 56 56 /* See Table 7 of xHCI specification */ 57 return SETUP_REQUEST_TYPE_IS_DEVICE_TO_HOST(bmRequestType) && (wLength > 0) 58 ? STAGE_OUT59 :STAGE_IN;57 return SETUP_REQUEST_TYPE_IS_DEVICE_TO_HOST(bmRequestType) && (wLength > 0) ? 58 STAGE_OUT : 59 STAGE_IN; 60 60 } 61 61 … … 69 69 * See Table 8 of xHCI specification. 70 70 */ 71 static inline data_stage_type_t get_transfer_type(xhci_trb_t *trb, uint8_t72 71 static inline data_stage_type_t get_transfer_type(xhci_trb_t *trb, uint8_t 72 bmRequestType, uint16_t wLength) 73 73 { 74 74 if (wLength == 0) … … 76 76 77 77 /* See Table 7 of xHCI specification */ 78 return SETUP_REQUEST_TYPE_IS_DEVICE_TO_HOST(bmRequestType) 79 ? DATA_STAGE_IN80 :DATA_STAGE_NO;78 return SETUP_REQUEST_TYPE_IS_DEVICE_TO_HOST(bmRequestType) ? 79 DATA_STAGE_IN : 80 DATA_STAGE_NO; 81 81 } 82 82 … … 86 86 87 87 return request_type == USB_REQUEST_TYPE_STANDARD && 88 (setup->request == USB_DEVREQ_SET_CONFIGURATION89 ||setup->request == USB_DEVREQ_SET_INTERFACE);88 (setup->request == USB_DEVREQ_SET_CONFIGURATION || 89 setup->request == USB_DEVREQ_SET_INTERFACE); 90 90 } 91 91 … … 95 95 * Bus callback. 96 96 */ 97 usb_transfer_batch_t * xhci_transfer_create(endpoint_t*ep)97 usb_transfer_batch_t *xhci_transfer_create(endpoint_t *ep) 98 98 { 99 99 xhci_transfer_t *transfer = calloc(1, sizeof(xhci_transfer_t)); … … 108 108 * Destroy a xHCI transfer. 109 109 */ 110 void xhci_transfer_destroy(usb_transfer_batch_t *batch)110 void xhci_transfer_destroy(usb_transfer_batch_t *batch) 111 111 { 112 112 xhci_transfer_t *transfer = xhci_transfer_from_batch(batch); … … 137 137 138 138 const size_t chunk_mask = dma_policy_chunk_mask(ts->buf.policy); 139 ts->chunk_size = (chunk_mask > MAX_CHUNK_SIZE + 1) 140 ?MAX_CHUNK_SIZE : (chunk_mask + 1);139 ts->chunk_size = (chunk_mask > MAX_CHUNK_SIZE + 1) ? 140 MAX_CHUNK_SIZE : (chunk_mask + 1); 141 141 142 142 ts->remaining = transfer->batch.size; … … 183 183 } 184 184 185 static errno_t schedule_control(xhci_hc_t * hc, xhci_transfer_t*transfer)185 static errno_t schedule_control(xhci_hc_t *hc, xhci_transfer_t *transfer) 186 186 { 187 187 usb_transfer_batch_t *batch = &transfer->batch; 188 188 xhci_endpoint_t *xhci_ep = xhci_endpoint_get(transfer->batch.ep); 189 189 190 usb_device_request_setup_packet_t *setup = &batch->setup.packet;190 usb_device_request_setup_packet_t *setup = &batch->setup.packet; 191 191 192 192 trb_splitter_t splitter; … … 210 210 get_transfer_type(trb_setup, setup->request_type, setup->length)); 211 211 212 stage_dir_flag_t stage_dir = (transfer->batch.dir == USB_DIRECTION_IN) 213 ?STAGE_IN : STAGE_OUT;212 stage_dir_flag_t stage_dir = (transfer->batch.dir == USB_DIRECTION_IN) ? 213 STAGE_IN : STAGE_OUT; 214 214 215 215 /* Data stage - first TRB is special */ … … 243 243 } 244 244 245 static errno_t schedule_bulk_intr(xhci_hc_t *hc, xhci_transfer_t *transfer)246 { 247 xhci_trb_ring_t * 245 static errno_t schedule_bulk_intr(xhci_hc_t *hc, xhci_transfer_t *transfer) 246 { 247 xhci_trb_ring_t *const ring = get_ring(transfer); 248 248 if (!ring) 249 249 return EINVAL; … … 266 266 /* Set the interrupt bit for last TRB */ 267 267 TRB_CTRL_SET_IOC(trbs[trbs_used - 1], 1); 268 } 269 else { 268 } else { 270 269 /* Clear the chain bit on the last TRB */ 271 270 TRB_CTRL_SET_CHAIN(trbs[trbs_used - 1], 1); … … 280 279 281 280 return xhci_trb_ring_enqueue_multiple(ring, trbs, trbs_used, 282 283 } 284 285 static int schedule_isochronous(xhci_transfer_t *transfer)281 &transfer->interrupt_trb_phys); 282 } 283 284 static int schedule_isochronous(xhci_transfer_t *transfer) 286 285 { 287 286 endpoint_t *ep = transfer->batch.ep; 288 287 289 return ep->direction == USB_DIRECTION_OUT 290 ? isoch_schedule_out(transfer)291 :isoch_schedule_in(transfer);292 } 293 294 errno_t xhci_handle_transfer_event(xhci_hc_t * hc, xhci_trb_t*trb)288 return ep->direction == USB_DIRECTION_OUT ? 289 isoch_schedule_out(transfer) : 290 isoch_schedule_in(transfer); 291 } 292 293 errno_t xhci_handle_transfer_event(xhci_hc_t *hc, xhci_trb_t *trb) 295 294 { 296 295 uintptr_t addr = trb->parameter; … … 327 326 transfer->interrupt_trb_phys); 328 327 batch = &transfer->batch; 329 } 330 else { 328 } else { 331 329 xhci_trb_ring_update_dequeue(&ep->ring, addr); 332 330 … … 354 352 const xhci_trb_completion_code_t completion_code = TRB_COMPLETION_CODE(*trb); 355 353 switch (completion_code) { 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 354 case XHCI_TRBC_SHORT_PACKET: 355 case XHCI_TRBC_SUCCESS: 356 batch->error = EOK; 357 batch->transferred_size = batch->size - TRB_TRANSFER_LENGTH(*trb); 358 break; 359 360 case XHCI_TRBC_DATA_BUFFER_ERROR: 361 usb_log_warning("Transfer ended with data buffer error."); 362 batch->error = EAGAIN; 363 batch->transferred_size = 0; 364 break; 365 366 case XHCI_TRBC_BABBLE_DETECTED_ERROR: 367 usb_log_warning("Babble detected during the transfer."); 368 batch->error = EAGAIN; 369 batch->transferred_size = 0; 370 break; 371 372 case XHCI_TRBC_USB_TRANSACTION_ERROR: 373 usb_log_warning("USB Transaction error."); 374 batch->error = EAGAIN; 375 batch->transferred_size = 0; 376 break; 377 378 case XHCI_TRBC_TRB_ERROR: 379 usb_log_error("Invalid transfer parameters."); 380 batch->error = EINVAL; 381 batch->transferred_size = 0; 382 break; 383 384 case XHCI_TRBC_STALL_ERROR: 385 usb_log_warning("Stall condition detected."); 386 batch->error = ESTALL; 387 batch->transferred_size = 0; 388 break; 389 390 case XHCI_TRBC_SPLIT_TRANSACTION_ERROR: 391 usb_log_error("Split transcation error detected."); 392 batch->error = EAGAIN; 393 batch->transferred_size = 0; 394 break; 395 396 default: 397 usb_log_warning("Transfer not successfull: %u", completion_code); 398 batch->error = EIO; 401 399 } 402 400 … … 456 454 * the Reset Endpoint command. 457 455 */ 458 if (batch->ep->transfer_type == USB_TRANSFER_CONTROL 459 &&batch->dir == USB_DIRECTION_OUT) {456 if (batch->ep->transfer_type == USB_TRANSFER_CONTROL && 457 batch->dir == USB_DIRECTION_OUT) { 460 458 const usb_device_request_setup_packet_t *request = &batch->setup.packet; 461 if (request->request == USB_DEVREQ_CLEAR_FEATURE 462 && request->request_type == USB_REQUEST_RECIPIENT_ENDPOINT463 &&request->value == USB_FEATURE_ENDPOINT_HALT) {459 if (request->request == USB_DEVREQ_CLEAR_FEATURE && 460 request->request_type == USB_REQUEST_RECIPIENT_ENDPOINT && 461 request->value == USB_FEATURE_ENDPOINT_HALT) { 464 462 const uint16_t index = uint16_usb2host(request->index); 465 463 const usb_endpoint_t ep_num = index & 0xf; 466 const usb_direction_t dir = (index >> 7) 467 ? USB_DIRECTION_IN468 :USB_DIRECTION_OUT;464 const usb_direction_t dir = (index >> 7) ? 465 USB_DIRECTION_IN : 466 USB_DIRECTION_OUT; 469 467 endpoint_t *halted_ep = bus_find_endpoint(&xhci_dev->base, ep_num, dir); 470 468 if (halted_ep) { … … 488 486 } else { 489 487 usb_log_warning("Device(%u): Resetting unregistered endpoint" 490 491 488 " %u %s.", xhci_dev->base.address, ep_num, 489 usb_str_direction(dir)); 492 490 } 493 491 } -
uspace/drv/bus/usb/xhci/trb_ring.c
r76d0981d r3bacee1 122 122 123 123 list_initialize(&ring->segments); 124 size_t segment_count = (initial_size + SEGMENT_TRB_USEFUL_COUNT - 1) 125 /SEGMENT_TRB_USEFUL_COUNT;124 size_t segment_count = (initial_size + SEGMENT_TRB_USEFUL_COUNT - 1) / 125 SEGMENT_TRB_USEFUL_COUNT; 126 126 127 127 for (size_t i = 0; i < segment_count; ++i) { … … 134 134 } 135 135 136 trb_segment_t * 136 trb_segment_t *const segment = get_first_segment(&ring->segments); 137 137 xhci_trb_t *last = segment_end(segment) - 1; 138 138 xhci_trb_link_fill(last, segment->phys); … … 198 198 static bool trb_generates_interrupt(xhci_trb_t *trb) 199 199 { 200 return TRB_TYPE(*trb) >= XHCI_TRB_TYPE_ENABLE_SLOT_CMD 201 ||TRB_IOC(*trb);200 return TRB_TYPE(*trb) >= XHCI_TRB_TYPE_ENABLE_SLOT_CMD || 201 TRB_IOC(*trb); 202 202 } 203 203 … … 220 220 */ 221 221 errno_t xhci_trb_ring_enqueue_multiple(xhci_trb_ring_t *ring, xhci_trb_t *first_trb, 222 222 size_t trbs, uintptr_t *phys) 223 223 { 224 224 errno_t err; … … 230 230 fibril_mutex_lock(&ring->guard); 231 231 232 xhci_trb_t * 233 trb_segment_t * 232 xhci_trb_t *const saved_enqueue_trb = ring->enqueue_trb; 233 trb_segment_t *const saved_enqueue_segment = ring->enqueue_segment; 234 234 if (phys) 235 235 *phys = (uintptr_t)NULL; … … 365 365 { 366 366 list_foreach(ring->segments, segments_link, trb_segment_t, segment) 367 368 369 trb_segment_t * 367 memset(segment->trb_storage, 0, sizeof(segment->trb_storage)); 368 369 trb_segment_t *const segment = get_first_segment(&ring->segments); 370 370 ring->dequeue_segment = segment; 371 371 ring->dequeue_trb = segment_begin(segment);
Note:
See TracChangeset
for help on using the changeset viewer.
