Changeset 3bacee1 in mainline for kernel/arch/sparc64
- Timestamp:
- 2018-04-12T16:27:17Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3cf22f9
- Parents:
- 76d0981d
- git-author:
- Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)
- Location:
- kernel/arch/sparc64
- Files:
-
- 3 edited
-
include/arch/asm.h (modified) (26 diffs)
-
src/fpu_context.c (modified) (4 diffs)
-
src/sun4v/md.c (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/include/arch/asm.h
r76d0981d r3bacee1 93 93 94 94 asm volatile ( 95 "rdpr %%pstate, %[v]\n"96 : [v] "=r" (v)95 "rdpr %%pstate, %[v]\n" 96 : [v] "=r" (v) 97 97 ); 98 98 … … 108 108 { 109 109 asm volatile ( 110 "wrpr %[v], %[zero], %%pstate\n"111 :: [v] "r" (v),112 [zero] "i" (0)110 "wrpr %[v], %[zero], %%pstate\n" 111 :: [v] "r" (v), 112 [zero] "i" (0) 113 113 ); 114 114 } … … 124 124 125 125 asm volatile ( 126 "rd %%tick_cmpr, %[v]\n"127 : [v] "=r" (v)126 "rd %%tick_cmpr, %[v]\n" 127 : [v] "=r" (v) 128 128 ); 129 129 … … 139 139 { 140 140 asm volatile ( 141 "wr %[v], %[zero], %%tick_cmpr\n"142 :: [v] "r" (v),143 [zero] "i" (0)141 "wr %[v], %[zero], %%tick_cmpr\n" 142 :: [v] "r" (v), 143 [zero] "i" (0) 144 144 ); 145 145 } … … 155 155 156 156 asm volatile ( 157 "rd %%asr25, %[v]\n"158 : [v] "=r" (v)157 "rd %%asr25, %[v]\n" 158 : [v] "=r" (v) 159 159 ); 160 160 … … 170 170 { 171 171 asm volatile ( 172 "wr %[v], %[zero], %%asr25\n"173 :: [v] "r" (v),174 [zero] "i" (0)172 "wr %[v], %[zero], %%asr25\n" 173 :: [v] "r" (v), 174 [zero] "i" (0) 175 175 ); 176 176 } … … 186 186 187 187 asm volatile ( 188 "rdpr %%tick, %[v]\n"189 : [v] "=r" (v)188 "rdpr %%tick, %[v]\n" 189 : [v] "=r" (v) 190 190 ); 191 191 … … 201 201 { 202 202 asm volatile ( 203 "wrpr %[v], %[zero], %%tick\n"204 :: [v] "r" (v),205 [zero] "i" (0)203 "wrpr %[v], %[zero], %%tick\n" 204 :: [v] "r" (v), 205 [zero] "i" (0) 206 206 ); 207 207 } … … 217 217 218 218 asm volatile ( 219 "rd %%fprs, %[v]\n"220 : [v] "=r" (v)219 "rd %%fprs, %[v]\n" 220 : [v] "=r" (v) 221 221 ); 222 222 … … 232 232 { 233 233 asm volatile ( 234 "wr %[v], %[zero], %%fprs\n"235 :: [v] "r" (v),236 [zero] "i" (0)234 "wr %[v], %[zero], %%fprs\n" 235 :: [v] "r" (v), 236 [zero] "i" (0) 237 237 ); 238 238 } … … 248 248 249 249 asm volatile ( 250 "rd %%softint, %[v]\n"251 : [v] "=r" (v)250 "rd %%softint, %[v]\n" 251 : [v] "=r" (v) 252 252 ); 253 253 … … 263 263 { 264 264 asm volatile ( 265 "wr %[v], %[zero], %%softint\n"266 :: [v] "r" (v),267 [zero] "i" (0)265 "wr %[v], %[zero], %%softint\n" 266 :: [v] "r" (v), 267 [zero] "i" (0) 268 268 ); 269 269 } … … 279 279 { 280 280 asm volatile ( 281 "wr %[v], %[zero], %%clear_softint\n"282 :: [v] "r" (v),283 [zero] "i" (0)281 "wr %[v], %[zero], %%clear_softint\n" 282 :: [v] "r" (v), 283 [zero] "i" (0) 284 284 ); 285 285 } … … 295 295 { 296 296 asm volatile ( 297 "wr %[v], %[zero], %%set_softint\n"298 :: [v] "r" (v),299 [zero] "i" (0)297 "wr %[v], %[zero], %%set_softint\n" 298 :: [v] "r" (v), 299 [zero] "i" (0) 300 300 ); 301 301 } … … 309 309 * 310 310 */ 311 NO_TRACE static inline ipl_t interrupts_enable(void) { 311 NO_TRACE static inline ipl_t interrupts_enable(void) 312 { 312 313 pstate_reg_t pstate; 313 314 uint64_t value = pstate_read(); … … 328 329 * 329 330 */ 330 NO_TRACE static inline ipl_t interrupts_disable(void) { 331 NO_TRACE static inline ipl_t interrupts_disable(void) 332 { 331 333 pstate_reg_t pstate; 332 334 uint64_t value = pstate_read(); … … 346 348 * 347 349 */ 348 NO_TRACE static inline void interrupts_restore(ipl_t ipl) { 350 NO_TRACE static inline void interrupts_restore(ipl_t ipl) 351 { 349 352 pstate_reg_t pstate; 350 353 … … 361 364 * 362 365 */ 363 NO_TRACE static inline ipl_t interrupts_read(void) { 366 NO_TRACE static inline ipl_t interrupts_read(void) 367 { 364 368 return (ipl_t) pstate_read(); 365 369 } … … 390 394 391 395 asm volatile ( 392 "add %%sp, %[stack_bias], %[unbiased_sp]\n"393 : [unbiased_sp] "=r" (unbiased_sp)394 : [stack_bias] "i" (STACK_BIAS)396 "add %%sp, %[stack_bias], %[unbiased_sp]\n" 397 : [unbiased_sp] "=r" (unbiased_sp) 398 : [stack_bias] "i" (STACK_BIAS) 395 399 ); 396 400 … … 408 412 409 413 asm volatile ( 410 "rdpr %%ver, %[v]\n"411 : [v] "=r" (v)414 "rdpr %%ver, %[v]\n" 415 : [v] "=r" (v) 412 416 ); 413 417 … … 425 429 426 430 asm volatile ( 427 "rdpr %%tpc, %[v]\n"428 : [v] "=r" (v)431 "rdpr %%tpc, %[v]\n" 432 : [v] "=r" (v) 429 433 ); 430 434 … … 442 446 443 447 asm volatile ( 444 "rdpr %%tl, %[v]\n"445 : [v] "=r" (v)448 "rdpr %%tl, %[v]\n" 449 : [v] "=r" (v) 446 450 ); 447 451 … … 459 463 460 464 asm volatile ( 461 "rdpr %%tba, %[v]\n"462 : [v] "=r" (v)465 "rdpr %%tba, %[v]\n" 466 : [v] "=r" (v) 463 467 ); 464 468 … … 474 478 { 475 479 asm volatile ( 476 "wrpr %[v], %[zero], %%tba\n"477 :: [v] "r" (v),478 [zero] "i" (0)480 "wrpr %[v], %[zero], %%tba\n" 481 :: [v] "r" (v), 482 [zero] "i" (0) 479 483 ); 480 484 } … … 494 498 495 499 asm volatile ( 496 "ldxa [%[va]] %[asi], %[v]\n"497 : [v] "=r" (v)498 : [va] "r" (va),499 [asi] "i" ((unsigned int) asi)500 "ldxa [%[va]] %[asi], %[v]\n" 501 : [v] "=r" (v) 502 : [va] "r" (va), 503 [asi] "i" ((unsigned int) asi) 500 504 ); 501 505 … … 513 517 { 514 518 asm volatile ( 515 "stxa %[v], [%[va]] %[asi]\n"516 :: [v] "r" (v),517 [va] "r" (va),518 [asi] "i" ((unsigned int) asi)519 : "memory"519 "stxa %[v], [%[va]] %[asi]\n" 520 :: [v] "r" (v), 521 [va] "r" (va), 522 [asi] "i" ((unsigned int) asi) 523 : "memory" 520 524 ); 521 525 } -
kernel/arch/sparc64/src/fpu_context.c
r76d0981d r3bacee1 41 41 { 42 42 asm volatile ( 43 "std %%f0, %0\n"44 "std %%f2, %1\n"45 "std %%f4, %2\n"46 "std %%f6, %3\n"47 "std %%f8, %4\n"48 "std %%f10, %5\n"49 "std %%f12, %6\n"50 "std %%f14, %7\n"51 "std %%f16, %8\n"52 "std %%f18, %9\n"53 "std %%f20, %10\n"54 "std %%f22, %11\n"55 "std %%f24, %12\n"56 "std %%f26, %13\n"57 "std %%f28, %14\n"58 "std %%f30, %15\n"59 : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),60 "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),61 "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),62 "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])43 "std %%f0, %0\n" 44 "std %%f2, %1\n" 45 "std %%f4, %2\n" 46 "std %%f6, %3\n" 47 "std %%f8, %4\n" 48 "std %%f10, %5\n" 49 "std %%f12, %6\n" 50 "std %%f14, %7\n" 51 "std %%f16, %8\n" 52 "std %%f18, %9\n" 53 "std %%f20, %10\n" 54 "std %%f22, %11\n" 55 "std %%f24, %12\n" 56 "std %%f26, %13\n" 57 "std %%f28, %14\n" 58 "std %%f30, %15\n" 59 : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]), 60 "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]), 61 "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]), 62 "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15]) 63 63 ); 64 64 … … 69 69 70 70 asm volatile ( 71 "std %%f32, %0\n"72 "std %%f34, %1\n"73 "std %%f36, %2\n"74 "std %%f38, %3\n"75 "std %%f40, %4\n"76 "std %%f42, %5\n"77 "std %%f44, %6\n"78 "std %%f46, %7\n"79 "std %%f48, %8\n"80 "std %%f50, %9\n"81 "std %%f52, %10\n"82 "std %%f54, %11\n"83 "std %%f56, %12\n"84 "std %%f58, %13\n"85 "std %%f60, %14\n"86 "std %%f62, %15\n"87 : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),88 "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),89 "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),90 "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])71 "std %%f32, %0\n" 72 "std %%f34, %1\n" 73 "std %%f36, %2\n" 74 "std %%f38, %3\n" 75 "std %%f40, %4\n" 76 "std %%f42, %5\n" 77 "std %%f44, %6\n" 78 "std %%f46, %7\n" 79 "std %%f48, %8\n" 80 "std %%f50, %9\n" 81 "std %%f52, %10\n" 82 "std %%f54, %11\n" 83 "std %%f56, %12\n" 84 "std %%f58, %13\n" 85 "std %%f60, %14\n" 86 "std %%f62, %15\n" 87 : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]), 88 "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]), 89 "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]), 90 "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31]) 91 91 ); 92 92 … … 97 97 { 98 98 asm volatile ( 99 "ldd %0, %%f0\n"100 "ldd %1, %%f2\n"101 "ldd %2, %%f4\n"102 "ldd %3, %%f6\n"103 "ldd %4, %%f8\n"104 "ldd %5, %%f10\n"105 "ldd %6, %%f12\n"106 "ldd %7, %%f14\n"107 "ldd %8, %%f16\n"108 "ldd %9, %%f18\n"109 "ldd %10, %%f20\n"110 "ldd %11, %%f22\n"111 "ldd %12, %%f24\n"112 "ldd %13, %%f26\n"113 "ldd %14, %%f28\n"114 "ldd %15, %%f30\n"115 :116 : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]),117 "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]),118 "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]),119 "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15])99 "ldd %0, %%f0\n" 100 "ldd %1, %%f2\n" 101 "ldd %2, %%f4\n" 102 "ldd %3, %%f6\n" 103 "ldd %4, %%f8\n" 104 "ldd %5, %%f10\n" 105 "ldd %6, %%f12\n" 106 "ldd %7, %%f14\n" 107 "ldd %8, %%f16\n" 108 "ldd %9, %%f18\n" 109 "ldd %10, %%f20\n" 110 "ldd %11, %%f22\n" 111 "ldd %12, %%f24\n" 112 "ldd %13, %%f26\n" 113 "ldd %14, %%f28\n" 114 "ldd %15, %%f30\n" 115 : 116 : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]), 117 "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]), 118 "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]), 119 "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15]) 120 120 ); 121 121 … … 126 126 127 127 asm volatile ( 128 "ldd %0, %%f32\n"129 "ldd %1, %%f34\n"130 "ldd %2, %%f36\n"131 "ldd %3, %%f38\n"132 "ldd %4, %%f40\n"133 "ldd %5, %%f42\n"134 "ldd %6, %%f44\n"135 "ldd %7, %%f46\n"136 "ldd %8, %%f48\n"137 "ldd %9, %%f50\n"138 "ldd %10, %%f52\n"139 "ldd %11, %%f54\n"140 "ldd %12, %%f56\n"141 "ldd %13, %%f58\n"142 "ldd %14, %%f60\n"143 "ldd %15, %%f62\n"144 :145 : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]),146 "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),147 "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),148 "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])128 "ldd %0, %%f32\n" 129 "ldd %1, %%f34\n" 130 "ldd %2, %%f36\n" 131 "ldd %3, %%f38\n" 132 "ldd %4, %%f40\n" 133 "ldd %5, %%f42\n" 134 "ldd %6, %%f44\n" 135 "ldd %7, %%f46\n" 136 "ldd %8, %%f48\n" 137 "ldd %9, %%f50\n" 138 "ldd %10, %%f52\n" 139 "ldd %11, %%f54\n" 140 "ldd %12, %%f56\n" 141 "ldd %13, %%f58\n" 142 "ldd %14, %%f60\n" 143 "ldd %15, %%f62\n" 144 : 145 : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]), 146 "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]), 147 "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]), 148 "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31]) 149 149 ); 150 150 -
kernel/arch/sparc64/src/sun4v/md.c
r76d0981d r3bacee1 62 62 uint32_t name_blk_sz; /**< Size in bytes of name block */ 63 63 uint32_t data_blk_sz; /**< Size in bytes of data block */ 64 } __attribute__ ((packed)) md_header_t;64 } __attribute__((packed)) md_header_t; 65 65 66 66 /** machine description element (in the node block) */ … … 91 91 uint64_t val; 92 92 } d; 93 } __attribute__ ((packed)) md_element_t;93 } __attribute__((packed)) md_element_t; 94 94 95 95 /** index of the element within the node block */ … … 98 98 /** buffer to which the machine description will be saved */ 99 99 static uint8_t mach_desc[MD_MAX_SIZE] 100 __attribute__ ((aligned(16)));100 __attribute__((aligned(16))); 101 101 102 102 … … 129 129 */ 130 130 bool md_get_integer_property(md_node_t node, const char *key, 131 uint64_t *result)131 uint64_t *result) 132 132 { 133 133 element_idx_t idx = node; … … 152 152 */ 153 153 bool md_get_string_property(md_node_t node, const char *key, 154 const char **result)154 const char **result) 155 155 { 156 156 md_header_t *md_header = (md_header_t *) mach_desc;
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