Changeset 3bacee1 in mainline for kernel/arch/ia32/include
- Timestamp:
- 2018-04-12T16:27:17Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3cf22f9
- Parents:
- 76d0981d
- git-author:
- Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)
- File:
-
- 1 edited
-
kernel/arch/ia32/include/arch/asm.h (modified) (19 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia32/include/arch/asm.h
r76d0981d r3bacee1 52 52 while (true) { 53 53 asm volatile ( 54 "hlt\n"54 "hlt\n" 55 55 ); 56 56 } … … 60 60 { 61 61 asm volatile ( 62 "hlt\n"62 "hlt\n" 63 63 ); 64 64 } … … 117 117 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) { 118 118 asm volatile ( 119 "outb %b[val], %w[port]\n"120 :: [val] "a" (val), [port] "d" (port)119 "outb %b[val], %w[port]\n" 120 :: [val] "a" (val), [port] "d" (port) 121 121 ); 122 122 } else … … 136 136 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) { 137 137 asm volatile ( 138 "outw %w[val], %w[port]\n"139 :: [val] "a" (val), [port] "d" (port)138 "outw %w[val], %w[port]\n" 139 :: [val] "a" (val), [port] "d" (port) 140 140 ); 141 141 } else … … 155 155 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) { 156 156 asm volatile ( 157 "outl %[val], %w[port]\n"158 :: [val] "a" (val), [port] "d" (port)157 "outl %[val], %w[port]\n" 158 :: [val] "a" (val), [port] "d" (port) 159 159 ); 160 160 } else … … 176 176 177 177 asm volatile ( 178 "inb %w[port], %b[val]\n"179 : [val] "=a" (val)180 : [port] "d" (port)178 "inb %w[port], %b[val]\n" 179 : [val] "=a" (val) 180 : [port] "d" (port) 181 181 ); 182 182 … … 200 200 201 201 asm volatile ( 202 "inw %w[port], %w[val]\n"203 : [val] "=a" (val)204 : [port] "d" (port)202 "inw %w[port], %w[val]\n" 203 : [val] "=a" (val) 204 : [port] "d" (port) 205 205 ); 206 206 … … 224 224 225 225 asm volatile ( 226 "inl %w[port], %[val]\n"227 : [val] "=a" (val)228 : [port] "d" (port)226 "inl %w[port], %[val]\n" 227 : [val] "=a" (val) 228 : [port] "d" (port) 229 229 ); 230 230 … … 239 239 240 240 asm volatile ( 241 "pushf\n"242 "popl %[v]\n"243 : [v] "=r" (eflags)241 "pushf\n" 242 "popl %[v]\n" 243 : [v] "=r" (eflags) 244 244 ); 245 245 … … 250 250 { 251 251 asm volatile ( 252 "pushl %[v]\n"253 "popf\n"254 :: [v] "r" (eflags)252 "pushl %[v]\n" 253 "popf\n" 254 :: [v] "r" (eflags) 255 255 ); 256 256 } … … 326 326 { 327 327 asm volatile ( 328 "wrmsr"329 :: "c" (msr),330 "a" ((uint32_t) (value)),331 "d" ((uint32_t) (value >> 32))328 "wrmsr" 329 :: "c" (msr), 330 "a" ((uint32_t) (value)), 331 "d" ((uint32_t) (value >> 32)) 332 332 ); 333 333 } … … 338 338 339 339 asm volatile ( 340 "rdmsr"341 : "=a" (ax),342 "=d" (dx)343 : "c" (msr)340 "rdmsr" 341 : "=a" (ax), 342 "=d" (dx) 343 : "c" (msr) 344 344 ); 345 345 … … 362 362 363 363 asm volatile ( 364 "andl %%esp, %[v]\n"365 : [v] "=r" (v)366 : "0" (~(STACK_SIZE - 1))364 "andl %%esp, %[v]\n" 365 : [v] "=r" (v) 366 : "0" (~(STACK_SIZE - 1)) 367 367 ); 368 368 … … 378 378 { 379 379 asm volatile ( 380 "invlpg %[addr]\n"381 :: [addr] "m" (*(sysarg_t *) addr)380 "invlpg %[addr]\n" 381 :: [addr] "m" (*(sysarg_t *) addr) 382 382 ); 383 383 } … … 391 391 { 392 392 asm volatile ( 393 "lgdtl %[gdtr_reg]\n"394 :: [gdtr_reg] "m" (*gdtr_reg)393 "lgdtl %[gdtr_reg]\n" 394 :: [gdtr_reg] "m" (*gdtr_reg) 395 395 ); 396 396 } … … 404 404 { 405 405 asm volatile ( 406 "sgdtl %[gdtr_reg]\n"407 : [gdtr_reg] "=m" (*gdtr_reg)406 "sgdtl %[gdtr_reg]\n" 407 : [gdtr_reg] "=m" (*gdtr_reg) 408 408 ); 409 409 } … … 417 417 { 418 418 asm volatile ( 419 "lidtl %[idtr_reg]\n"420 :: [idtr_reg] "m" (*idtr_reg)419 "lidtl %[idtr_reg]\n" 420 :: [idtr_reg] "m" (*idtr_reg) 421 421 ); 422 422 } … … 430 430 { 431 431 asm volatile ( 432 "ltr %[sel]"433 :: [sel] "r" (sel)432 "ltr %[sel]" 433 :: [sel] "r" (sel) 434 434 ); 435 435 } … … 443 443 { 444 444 asm volatile ( 445 "mov %[sel], %%gs"446 :: [sel] "r" (sel)445 "mov %[sel], %%gs" 446 :: [sel] "r" (sel) 447 447 ); 448 448 }
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