Changeset 38a1a84 in mainline for arch/mips32/include/mm/tlb.h

Timestamp:

2005-10-05T21:29:16Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bca1b47

Parents:

49c1f93

Message:

MIPS32 memory management work.
Fix some bugs introduced yesterday (PTL3 index is indeed calculated by >> 14).
Introduce two new bits in pte_t (i.e. 'a' and 'w').
Implement TLB Invalid Exception and TLB Modified Exception. (Needs review and testing)

File:

• arch/mips32/include/mm/tlb.h (modified) (2 diffs)

arch/mips32/include/mm/tlb.h

@@ -48 +48 @@
         unsigned c : 3;         /* cache coherency attribute */
         unsigned pfn : 24;      /* frame number */
-        unsigned : 2;
+        unsigned zero: 2;       /* zero */
+} __attribute__ ((packed));
+
+struct pte {
+        unsigned g : 1;         /* global bit */
+        unsigned v : 1;         /* valid bit */
+        unsigned d : 1;         /* dirty/write-protect bit */
+        unsigned c : 3;         /* cache coherency attribute */
+        unsigned pfn : 24;      /* frame number */
+        unsigned w : 1;         /* writable */
+        unsigned a : 1;         /* accessed */
 } __attribute__ ((packed));
 
@@ -63 +73 @@
 } __attribute__ ((packed));
 
-struct tlb_entry {
-        struct entry_lo lo0;
-        struct entry_lo lo1;
-        struct entry_hi hi;
-        struct page_mask mask;
+struct index {
+        unsigned index : 4;
+        unsigned : 27;
+        unsigned p : 1;
 } __attribute__ ((packed));
+
+/** Probe TLB for Matching Entry
+ *
+ * Probe TLB for Matching Entry.
+ */
+static inline void tlbp(void)
+{
+        __asm__ volatile ("tlbp\n\t");
+}