Changeset 38a1a84 in mainline for arch/mips32/include/mm/page.h

Timestamp:

2005-10-05T21:29:16Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bca1b47

Parents:

49c1f93

Message:

MIPS32 memory management work.
Fix some bugs introduced yesterday (PTL3 index is indeed calculated by >> 14).
Introduce two new bits in pte_t (i.e. 'a' and 'w').
Implement TLB Invalid Exception and TLB Modified Exception. (Needs review and testing)

File:

• arch/mips32/include/mm/page.h (modified) (4 diffs)

arch/mips32/include/mm/page.h

@@ -47 +47 @@
  * - 32-bit virtual addresses
  * - Offset is 14 bits => pages are 16K long
- * - PTE's use the same format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
+ * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
+ * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
  * - PTL0 has 64 entries (6 bits)
  * - PTL1 is not used
@@ -57 +58 @@
 #define PTL1_INDEX_ARCH(vaddr)  0
 #define PTL2_INDEX_ARCH(vaddr)  0
-#define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>12)&0xfff)
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>14)&0x3fff)
 
 #define GET_PTL0_ADDRESS_ARCH()                 (PTL0)
@@ -98 +99 @@
                 (1<<PAGE_USER_SHIFT) |
                 (1<<PAGE_READ_SHIFT) |
-                ((p->d)<<PAGE_WRITE_SHIFT) |
+                ((p->w)<<PAGE_WRITE_SHIFT) |
                 (1<<PAGE_EXEC_SHIFT)
         );
@@ -110 +111 @@
         p->c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
         p->v = !(flags & PAGE_NOT_PRESENT);
-        p->d = (flags & PAGE_WRITE) != 0;
+        p->w = (flags & PAGE_WRITE) != 0;
 }