Index: kernel/arch/ia64/src/mm/tlb.c
===================================================================
--- kernel/arch/ia64/src/mm/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/mm/tlb.c	(revision 34e1206ec4dc79f0592077e3ee270fba91d1eb9d)
@@ -61,7 +61,7 @@
 	uintptr_t adr;
 	uint32_t count1, count2, stride1, stride2;
-	
+
 	unsigned int i, j;
-	
+
 	adr = PAL_PTCE_INFO_BASE();
 	count1 = PAL_PTCE_INFO_COUNT1();
@@ -69,7 +69,7 @@
 	stride1 = PAL_PTCE_INFO_STRIDE1();
 	stride2 = PAL_PTCE_INFO_STRIDE2();
-	
+
 	ipl = interrupts_disable();
-	
+
 	for (i = 0; i < count1; i++) {
 		for (j = 0; j < count2; j++) {
@@ -82,10 +82,10 @@
 		adr += stride1;
 	}
-	
+
 	interrupts_restore(ipl);
-	
+
 	srlz_d();
 	srlz_i();
-	
+
 #ifdef CONFIG_VHPT
 	vhpt_invalidate_all();
@@ -110,8 +110,8 @@
 	int b = 0;
 	int c = cnt;
-	
+
 	uintptr_t va;
 	va = page;
-	
+
 	rr.word = rr_read(VA2VRN(page));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(page))))) {
@@ -121,5 +121,5 @@
 		 */
 		region_register_t rr0;
-		
+
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(page));
@@ -128,10 +128,10 @@
 		srlz_i();
 	}
-	
+
 	while (c >>= 1)
 		b++;
 	b >>= 1;
 	uint64_t ps;
-	
+
 	switch (b) {
 	case 0: /* cnt 1 - 3 */
@@ -172,5 +172,5 @@
 		break;
 	}
-	
+
 	for (; va < (page + cnt * PAGE_SIZE); va += (1UL << ps))
 		asm volatile (
@@ -179,8 +179,8 @@
 			   [ps] "r" (ps << 2)
 		);
-	
+
 	srlz_d();
 	srlz_i();
-	
+
 	if (restore_rr) {
 		rr_write(VA2VRN(page), rr.word);
@@ -229,5 +229,5 @@
 	region_register_t rr;
 	bool restore_rr = false;
-	
+
 	rr.word = rr_read(VA2VRN(va));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -237,5 +237,5 @@
 		 */
 		region_register_t rr0;
-		
+
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -244,5 +244,5 @@
 		srlz_i();
 	}
-	
+
 	asm volatile (
 		"mov r8 = psr ;;\n"
@@ -264,5 +264,5 @@
 		: "p6", "p7", "r8"
 	);
-	
+
 	if (restore_rr) {
 		rr_write(VA2VRN(va), rr.word);
@@ -316,5 +316,5 @@
 	region_register_t rr;
 	bool restore_rr = false;
-	
+
 	rr.word = rr_read(VA2VRN(va));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -324,5 +324,5 @@
 		 */
 		region_register_t rr0;
-		
+
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -331,5 +331,5 @@
 		srlz_i();
 	}
-	
+
 	asm volatile (
 		"mov r8 = psr ;;\n"
@@ -352,5 +352,5 @@
 		: "p6", "p7", "r8"
 	);
-	
+
 	if (restore_rr) {
 		rr_write(VA2VRN(va), rr.word);
@@ -373,8 +373,8 @@
 {
 	tlb_entry_t entry;
-	
+
 	entry.word[0] = 0;
 	entry.word[1] = 0;
-	
+
 	entry.p = true;           /* present */
 	entry.ma = MA_WRITEBACK;
@@ -385,5 +385,5 @@
 	entry.ppn = frame >> PPN_SHIFT;
 	entry.ps = PAGE_WIDTH;
-	
+
 	if (dtr)
 		dtr_mapping_insert(page, ASID_KERNEL, entry, tr);
@@ -418,8 +418,8 @@
 {
 	tlb_entry_t entry;
-	
+
 	entry.word[0] = 0;
 	entry.word[1] = 0;
-	
+
 	entry.p = t->p;
 	entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
@@ -430,7 +430,7 @@
 	entry.ppn = t->frame >> PPN_SHIFT;
 	entry.ps = PAGE_WIDTH;
-	
+
 	dtc_mapping_insert(t->page, t->as->asid, entry);
-	
+
 #ifdef CONFIG_VHPT
 	vhpt_mapping_insert(t->page, t->as->asid, entry);
@@ -446,10 +446,10 @@
 {
 	tlb_entry_t entry;
-	
+
 	entry.word[0] = 0;
 	entry.word[1] = 0;
-	
+
 	assert(t->x);
-	
+
 	entry.p = t->p;
 	entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
@@ -459,7 +459,7 @@
 	entry.ppn = t->frame >> PPN_SHIFT;
 	entry.ps = PAGE_WIDTH;
-	
+
 	itc_mapping_insert(t->page, t->as->asid, entry);
-	
+
 #ifdef CONFIG_VHPT
 	vhpt_mapping_insert(t->page, t->as->asid, entry);
@@ -486,7 +486,7 @@
 	uintptr_t va;
 	pte_t t;
-	
+
 	va = istate->cr_ifa; /* faulting address */
-	
+
 	assert(!is_kernel_fault(va));
 
@@ -532,18 +532,18 @@
 			uint64_t io_page = (va & ((1 << LEGACYIO_PAGE_WIDTH) - 1)) >>
 			    LEGACYIO_SINGLE_PAGE_WIDTH;
-			
+
 			if (is_io_page_accessible(io_page)) {
 				uint64_t page, frame;
-				
+
 				page = LEGACYIO_USER_BASE +
 				    (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page;
 				frame = LEGACYIO_PHYS_BASE +
 				    (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page;
-				
+
 				tlb_entry_t entry;
-				
+
 				entry.word[0] = 0;
 				entry.word[1] = 0;
-				
+
 				entry.p = true;             /* present */
 				entry.ma = MA_UNCACHEABLE;
@@ -554,5 +554,5 @@
 				entry.ppn = frame >> PPN_SHIFT;
 				entry.ps = LEGACYIO_SINGLE_PAGE_WIDTH;
-				
+
 				dtc_mapping_insert(page, TASK->as->asid, entry);
 				return 1;
@@ -563,5 +563,5 @@
 		}
 	}
-	
+
 	return 0;
 }
@@ -586,8 +586,8 @@
 		return;
 	}
-	
+
 	uintptr_t va = istate->cr_ifa;  /* faulting address */
 	as_t *as = AS;
-	
+
 	if (is_kernel_fault(va)) {
 		if (va < end_of_identity) {
@@ -601,6 +601,6 @@
 		}
 	}
-	
-	
+
+
 	pte_t t;
 	bool found = page_mapping_find(as, va, true, &t);
@@ -616,5 +616,5 @@
 		if (try_memmap_io_insertion(va, istate))
 			return;
-		
+
 		/*
 		 * Forward the page fault to the address space page fault
@@ -649,7 +649,7 @@
 	pte_t t;
 	as_t *as = AS;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
-	
+
 	if (is_kernel_fault(va))
 		as = AS_KERNEL;
@@ -683,9 +683,9 @@
 	uintptr_t va;
 	pte_t t;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
 
 	assert(!is_kernel_fault(va));
-	
+
 	bool found = page_mapping_find(AS, va, true, &t);
 
@@ -717,7 +717,7 @@
 	pte_t t;
 	as_t *as = AS;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
-	
+
 	if (is_kernel_fault(va))
 		as = AS_KERNEL;
@@ -755,9 +755,9 @@
 	uintptr_t va;
 	pte_t t;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
 
 	assert(!is_kernel_fault(va));
-	
+
 	/*
 	 * Assume a write to a read-only page.
@@ -782,7 +782,7 @@
 	uintptr_t va;
 	pte_t t;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
-	
+
 	assert(!is_kernel_fault(va));
 
@@ -790,5 +790,5 @@
 
 	assert(found);
-	
+
 	if (t.p) {
 		/*
