Index: kernel/arch/amd64/include/mm/page.h =================================================================== --- kernel/arch/amd64/include/mm/page.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/arch/amd64/include/mm/page.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -70,12 +70,13 @@ } -# define KA2PA(x) ka2pa((uintptr_t)x) -# define PA2KA_CODE(x) (((uintptr_t) (x)) + 0xffffffff80000000) -# define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000) +# define KA2PA(x) ka2pa((uintptr_t) x) +# define PA2KA_CODE(x) (((uintptr_t) (x)) + 0xffffffff80000000) +# define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000) #else -# define KA2PA(x) ((x) - 0xffffffff80000000) -# define PA2KA(x) ((x) + 0xffffffff80000000) +# define KA2PA(x) ((x) - 0xffffffff80000000) +# define PA2KA(x) ((x) + 0xffffffff80000000) #endif +/* Number of entries in each level. */ #define PTL0_ENTRIES_ARCH 512 #define PTL1_ENTRIES_ARCH 512 @@ -83,40 +84,75 @@ #define PTL3_ENTRIES_ARCH 512 -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH ONE_FRAME -#define PTL2_SIZE_ARCH ONE_FRAME -#define PTL3_SIZE_ARCH ONE_FRAME - -#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>39)&0x1ff) -#define PTL1_INDEX_ARCH(vaddr) (((vaddr)>>30)&0x1ff) -#define PTL2_INDEX_ARCH(vaddr) (((vaddr)>>21)&0x1ff) -#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0x1ff) - -#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 ))) -#define GET_PTL2_ADDRESS_ARCH(ptl1, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 ))) -#define GET_PTL3_ADDRESS_ARCH(ptl2, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 ))) -#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t *) ((((uint64_t) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 ))) - -#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((uintptr_t) (ptl0))) -#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) set_pt_addr((pte_t *)(ptl0), (index_t)(i), a) -#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) set_pt_addr((pte_t *)(ptl1), (index_t)(i), a) -#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) set_pt_addr((pte_t *)(ptl2), (index_t)(i), a) -#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) set_pt_addr((pte_t *)(ptl3), (index_t)(i), a) - -#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) -#define GET_PTL2_FLAGS_ARCH(ptl1, i) get_pt_flags((pte_t *)(ptl1), (index_t)(i)) -#define GET_PTL3_FLAGS_ARCH(ptl2, i) get_pt_flags((pte_t *)(ptl2), (index_t)(i)) -#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) - -#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x)) -#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) set_pt_flags((pte_t *)(ptl1), (index_t)(i), (x)) -#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) set_pt_flags((pte_t *)(ptl2), (index_t)(i), (x)) -#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) - -#define PTE_VALID_ARCH(p) (*((uint64_t *) (p)) != 0) -#define PTE_PRESENT_ARCH(p) ((p)->present != 0) -#define PTE_GET_FRAME_ARCH(p) ((((uintptr_t)(p)->addr_12_31)<<12) | ((uintptr_t)(p)->addr_32_51<<32)) -#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0) -#define PTE_EXECUTABLE_ARCH(p) ((p)->no_execute == 0) +/* Page table sizes for each level. */ +#define PTL0_SIZE_ARCH ONE_FRAME +#define PTL1_SIZE_ARCH ONE_FRAME +#define PTL2_SIZE_ARCH ONE_FRAME +#define PTL3_SIZE_ARCH ONE_FRAME + +/* Macros calculating indices into page tables in each level. */ +#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff) +#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff) +#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff) +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff) + +/* Get PTE address accessors for each level. */ +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ + ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \ + (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32))) +#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ + ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \ + (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32))) +#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ + ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \ + (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32))) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ + ((uintptr_t *) \ + ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \ + (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32))) + +/* Set PTE address accessors for each level. */ +#define SET_PTL0_ADDRESS_ARCH(ptl0) \ + (write_cr3((uintptr_t) (ptl0))) +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ + set_pt_addr((pte_t *) (ptl0), (index_t) (i), a) +#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \ + set_pt_addr((pte_t *) (ptl1), (index_t) (i), a) +#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \ + set_pt_addr((pte_t *) (ptl2), (index_t) (i), a) +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ + set_pt_addr((pte_t *) (ptl3), (index_t) (i), a) + +/* Get PTE flags accessors for each level. */ +#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ + get_pt_flags((pte_t *) (ptl0), (index_t) (i)) +#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ + get_pt_flags((pte_t *) (ptl1), (index_t) (i)) +#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ + get_pt_flags((pte_t *) (ptl2), (index_t) (i)) +#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ + get_pt_flags((pte_t *) (ptl3), (index_t) (i)) + +/* Set PTE flags accessors for each level. */ +#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ + set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) +#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \ + set_pt_flags((pte_t *) (ptl1), (index_t) (i), (x)) +#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \ + set_pt_flags((pte_t *) (ptl2), (index_t) (i), (x)) +#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ + set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(p) \ + (*((uint64_t *) (p)) != 0) +#define PTE_PRESENT_ARCH(p) \ + ((p)->present != 0) +#define PTE_GET_FRAME_ARCH(p) \ + ((((uintptr_t) (p)->addr_12_31) << 12) | \ + ((uintptr_t) (p)->addr_32_51 << 32)) +#define PTE_WRITABLE_ARCH(p) \ + ((p)->writeable != 0) +#define PTE_EXECUTABLE_ARCH(p) \ + ((p)->no_execute == 0) #ifndef __ASM__ @@ -124,18 +160,22 @@ /* Page fault error codes. */ -/** When bit on this position is 0, the page fault was caused by a not-present page. */ -#define PFERR_CODE_P (1<<0) +/** When bit on this position is 0, the page fault was caused by a not-present + * page. + */ +#define PFERR_CODE_P (1 << 0) /** When bit on this position is 1, the page fault was caused by a write. */ -#define PFERR_CODE_RW (1<<1) +#define PFERR_CODE_RW (1 << 1) /** When bit on this position is 1, the page fault was caused in user mode. */ -#define PFERR_CODE_US (1<<2) +#define PFERR_CODE_US (1 << 2) /** When bit on this position is 1, a reserved bit was set in page directory. */ -#define PFERR_CODE_RSVD (1<<3) - -/** When bit on this position os 1, the page fault was caused during instruction fecth. */ -#define PFERR_CODE_ID (1<<4) +#define PFERR_CODE_RSVD (1 << 3) + +/** When bit on this position os 1, the page fault was caused during instruction + * fecth. + */ +#define PFERR_CODE_ID (1 << 4) static inline int get_pt_flags(pte_t *pt, index_t i) @@ -143,13 +183,11 @@ pte_t *p = &pt[i]; - return ( - (!p->page_cache_disable)<present)<uaccessible<writeable<no_execute)<global<page_cache_disable) << PAGE_CACHEABLE_SHIFT | + (!p->present) << PAGE_PRESENT_SHIFT | + p->uaccessible << PAGE_USER_SHIFT | + 1 << PAGE_READ_SHIFT | + p->writeable << PAGE_WRITE_SHIFT | + (!p->no_execute) << PAGE_EXEC_SHIFT | + p->global << PAGE_GLOBAL_SHIFT); } Index: kernel/arch/arm32/include/mm/page.h =================================================================== --- kernel/arch/arm32/include/mm/page.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/arch/arm32/include/mm/page.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -56,11 +56,12 @@ #ifdef KERNEL +/* Number of entries in each level. */ #define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ #define PTL1_ENTRIES_ARCH 0 #define PTL2_ENTRIES_ARCH 0 - /* coarse page tables used (256 * 4 = 1KB per page) */ #define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ +/* Page table sizes for each level. */ #define PTL0_SIZE_ARCH FOUR_FRAMES #define PTL1_SIZE_ARCH 0 @@ -68,4 +69,5 @@ #define PTL3_SIZE_ARCH ONE_FRAME +/* Macros calculating indices into page tables for each level. */ #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) #define PTL1_INDEX_ARCH(vaddr) 0 @@ -73,4 +75,5 @@ #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) +/* Get PTE address accessors for each level. */ #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) @@ -82,4 +85,5 @@ ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) +/* Set PTE address accessors for each level. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) \ (set_ptl0_addr((pte_level0_t *) (ptl0))) @@ -91,4 +95,5 @@ (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) +/* Get PTE flags accessors for each level. */ #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) @@ -100,4 +105,5 @@ get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) +/* Set PTE flags accessors for each level. */ #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) @@ -107,18 +113,14 @@ set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) +/* Macros for querying the last-level PTE entries. */ #define PTE_VALID_ARCH(pte) \ (*((uint32_t *) (pte)) != 0) #define PTE_PRESENT_ARCH(pte) \ (((pte_level0_t *) (pte))->descriptor_type != 0) - -/* pte should point into ptl3 */ #define PTE_GET_FRAME_ARCH(pte) \ (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) - -/* pte should point into ptl3 */ #define PTE_WRITABLE_ARCH(pte) \ (((pte_level1_t *) (pte))->access_permission_0 == \ PTE_AP_USER_RW_KERNEL_RW) - #define PTE_EXECUTABLE_ARCH(pte) \ 1 @@ -129,8 +131,8 @@ typedef struct { /* 0b01 for coarse tables, see below for details */ - unsigned descriptor_type : 2; - unsigned impl_specific : 3; - unsigned domain : 4; - unsigned should_be_zero : 1; + unsigned descriptor_type : 2; + unsigned impl_specific : 3; + unsigned domain : 4; + unsigned should_be_zero : 1; /* Pointer to the coarse 2nd level page table (holding entries for small @@ -139,5 +141,5 @@ * per table in comparison with 1KB per the coarse table) */ - unsigned coarse_table_addr : 22; + unsigned coarse_table_addr : 22; } ATTRIBUTE_PACKED pte_level0_t; @@ -146,7 +148,7 @@ /* 0b10 for small pages */ - unsigned descriptor_type : 2; - unsigned bufferable : 1; - unsigned cacheable : 1; + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; /* access permissions for each of 4 subparts of a page @@ -156,5 +158,5 @@ unsigned access_permission_2 : 2; unsigned access_permission_3 : 2; - unsigned frame_base_addr : 20; + unsigned frame_base_addr : 20; } ATTRIBUTE_PACKED pte_level1_t; @@ -191,5 +193,5 @@ * @param pt Pointer to the page table to set. */ -static inline void set_ptl0_addr( pte_level0_t *pt) +static inline void set_ptl0_addr(pte_level0_t *pt) { asm volatile ( Index: kernel/arch/arm32/include/mm/page_fault.h =================================================================== --- kernel/arch/arm32/include/mm/page_fault.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/arch/arm32/include/mm/page_fault.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -42,8 +42,8 @@ /** Decribes CP15 "fault status register" (FSR). */ typedef struct { - unsigned status : 3; - unsigned domain : 4; - unsigned zero : 1; - unsigned should_be_zero : 24; + unsigned status : 3; + unsigned domain : 4; + unsigned zero : 1; + unsigned should_be_zero : 24; } ATTRIBUTE_PACKED fault_status_t; @@ -62,12 +62,12 @@ */ typedef struct { - unsigned dummy1 : 4; - unsigned bit4 : 1; - unsigned bits567 : 3; - unsigned dummy : 12; - unsigned access : 1; - unsigned opcode : 4; - unsigned type : 3; - unsigned condition : 4; + unsigned dummy1 : 4; + unsigned bit4 : 1; + unsigned bits567 : 3; + unsigned dummy : 12; + unsigned access : 1; + unsigned opcode : 4; + unsigned type : 3; + unsigned condition : 4; } ATTRIBUTE_PACKED instruction_t; Index: kernel/arch/ia32/include/mm/page.h =================================================================== --- kernel/arch/ia32/include/mm/page.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/arch/ia32/include/mm/page.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -57,4 +57,6 @@ * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out. */ + +/* Number of entries in each level. */ #define PTL0_ENTRIES_ARCH 1024 #define PTL1_ENTRIES_ARCH 0 @@ -62,9 +64,11 @@ #define PTL3_ENTRIES_ARCH 1024 -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +/* Page table sizes for each level. */ +#define PTL0_SIZE_ARCH ONE_FRAME +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME +/* Macros calculating indices for each level. */ #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) #define PTL1_INDEX_ARCH(vaddr) 0 @@ -72,29 +76,51 @@ #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff) -#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)((((pte_t *)(ptl0))[(i)].frame_address) << 12)) -#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) -#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) -#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)((((pte_t *)(ptl3))[(i)].frame_address) << 12)) +/* Get PTE address accessors for each level. */ +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ + ((pte_t *) ((((pte_t *) (ptl0))[(i)].frame_address) << 12)) +#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ + (ptl1) +#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ + (ptl2) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ + ((uintptr_t) ((((pte_t *) (ptl3))[(i)].frame_address) << 12)) -#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((uintptr_t) (ptl0))) -#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].frame_address = (a)>>12) +/* Set PTE address accessors for each level. */ +#define SET_PTL0_ADDRESS_ARCH(ptl0) \ + (write_cr3((uintptr_t) (ptl0))) +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ + (((pte_t *) (ptl0))[(i)].frame_address = (a) >> 12) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) -#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].frame_address = (a)>>12) +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ + (((pte_t *) (ptl3))[(i)].frame_address = (a) >> 12) -#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) -#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT -#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT -#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) +/* Get PTE flags accessors for each level. */ +#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ + get_pt_flags((pte_t *) (ptl0), (index_t) (i)) +#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ + PAGE_PRESENT +#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ + PAGE_PRESENT +#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ + get_pt_flags((pte_t *) (ptl3), (index_t) (i)) -#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x)) +/* Set PTE flags accessors for each level. */ +#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ + set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) -#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) +#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ + set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) -#define PTE_VALID_ARCH(p) (*((uint32_t *) (p)) != 0) -#define PTE_PRESENT_ARCH(p) ((p)->present != 0) -#define PTE_GET_FRAME_ARCH(p) ((p)->frame_address << FRAME_WIDTH) -#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0) +/* Macros for querying the last level entries. */ +#define PTE_VALID_ARCH(p) \ + (*((uint32_t *) (p)) != 0) +#define PTE_PRESENT_ARCH(p) \ + ((p)->present != 0) +#define PTE_GET_FRAME_ARCH(p) \ + ((p)->frame_address << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(p) \ + ((p)->writeable != 0) #define PTE_EXECUTABLE_ARCH(p) 1 @@ -106,5 +132,7 @@ /* Page fault error codes. */ -/** When bit on this position is 0, the page fault was caused by a not-present page. */ +/** When bit on this position is 0, the page fault was caused by a not-present + * page. + */ #define PFERR_CODE_P (1 << 0) @@ -122,13 +150,11 @@ pte_t *p = &pt[i]; - return ( - (!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | - (!p->present) << PAGE_PRESENT_SHIFT | - p->uaccessible << PAGE_USER_SHIFT | - 1<writeable << PAGE_WRITE_SHIFT | - 1<global << PAGE_GLOBAL_SHIFT - ); + return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | + (!p->present) << PAGE_PRESENT_SHIFT | + p->uaccessible << PAGE_USER_SHIFT | + 1 << PAGE_READ_SHIFT | + p->writeable << PAGE_WRITE_SHIFT | + 1 << PAGE_EXEC_SHIFT | + p->global << PAGE_GLOBAL_SHIFT); } @@ -144,5 +170,6 @@ /* - * Ensure that there is at least one bit set even if the present bit is cleared. + * Ensure that there is at least one bit set even if the present bit is + * cleared. */ p->soft_valid = true; Index: kernel/arch/ia32xen/include/mm/page.h =================================================================== --- kernel/arch/ia32xen/include/mm/page.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/arch/ia32xen/include/mm/page.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -57,4 +57,6 @@ * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out. */ + +/* Number of entries in each level. */ #define PTL0_ENTRIES_ARCH 1024 #define PTL1_ENTRIES_ARCH 0 @@ -62,9 +64,11 @@ #define PTL3_ENTRIES_ARCH 1024 -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME - +/* Page table size for each level. */ +#define PTL0_SIZE_ARCH ONE_FRAME +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME + +/* Macros calculating indices into page tables in each level. */ #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) #define PTL1_INDEX_ARCH(vaddr) 0 @@ -72,10 +76,17 @@ #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff) -#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12)) -#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) -#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) -#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12)) - -#define SET_PTL0_ADDRESS_ARCH(ptl0) { \ +/* Get PTE address accessors for each level. */ +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ + ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12)) +#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ + (ptl1) +#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ + (ptl2) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ + ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12)) + +/* Set PTE address accessors for each level. */ +#define SET_PTL0_ADDRESS_ARCH(ptl0) \ +{ \ mmuext_op_t mmu_ext; \ \ @@ -85,5 +96,6 @@ } -#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \ +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ +{ \ mmuext_op_t mmu_ext; \ \ @@ -101,5 +113,6 @@ #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) -#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \ +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ +{ \ mmu_update_t update; \ \ @@ -109,19 +122,33 @@ } -#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t)(i)) -#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT -#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT -#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t)(i)) - -#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t)(i), (x)) +/* Get PTE flags accessors for each level. */ +#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ + get_pt_flags((pte_t *) (ptl0), (index_t) (i)) +#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ + PAGE_PRESENT +#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ + PAGE_PRESENT +#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ + get_pt_flags((pte_t *) (ptl3), (index_t) (i)) + +/* Set PTE flags accessors for each level. */ +#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ + set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) -#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t)(i), (x)) - -#define PTE_VALID_ARCH(p) (*((uint32_t *) (p)) != 0) -#define PTE_PRESENT_ARCH(p) ((p)->present != 0) -#define PTE_GET_FRAME_ARCH(p) ((p)->frame_address << FRAME_WIDTH) -#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0) -#define PTE_EXECUTABLE_ARCH(p) 1 +#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ + set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) + +/* Query macros for the last level. */ +#define PTE_VALID_ARCH(p) \ + (*((uint32_t *) (p)) != 0) +#define PTE_PRESENT_ARCH(p) \ + ((p)->present != 0) +#define PTE_GET_FRAME_ARCH(p) \ + ((p)->frame_address << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(p) \ + ((p)->writeable != 0) +#define PTE_EXECUTABLE_ARCH(p) \ + 1 #ifndef __ASM__ @@ -133,5 +160,7 @@ /* Page fault error codes. */ -/** When bit on this position is 0, the page fault was caused by a not-present page. */ +/** When bit on this position is 0, the page fault was caused by a not-present + * page. + */ #define PFERR_CODE_P (1 << 0) @@ -165,15 +194,18 @@ } mmuext_op_t; -static inline int xen_update_va_mapping(const void *va, const pte_t pte, const unsigned int flags) +static inline int xen_update_va_mapping(const void *va, const pte_t pte, + const unsigned int flags) { return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags); } -static inline int xen_mmu_update(const mmu_update_t *req, const unsigned int count, unsigned int *success_count, domid_t domid) +static inline int xen_mmu_update(const mmu_update_t *req, + const unsigned int count, unsigned int *success_count, domid_t domid) { return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid); } -static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, unsigned int *success_count, domid_t domid) +static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, + unsigned int *success_count, domid_t domid) { return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid); @@ -184,13 +216,11 @@ pte_t *p = &pt[i]; - return ( - (!p->page_cache_disable)<present)<uaccessible<writeable<global<page_cache_disable) << PAGE_CACHEABLE_SHIFT | + (!p->present) << PAGE_PRESENT_SHIFT | + p->uaccessible << PAGE_USER_SHIFT | + 1 << PAGE_READ_SHIFT | + p->writeable << PAGE_WRITE_SHIFT | + 1 << PAGE_EXEC_SHIFT | + p->global << PAGE_GLOBAL_SHIFT); } Index: kernel/arch/mips32/include/mm/page.h =================================================================== --- kernel/arch/mips32/include/mm/page.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/arch/mips32/include/mm/page.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -59,9 +59,13 @@ * - 32-bit virtual addresses * - Offset is 14 bits => pages are 16K long - * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long + * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore + * 4 bytes long * - PTE's replace EntryLo v (valid) bit with p (present) bit - * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings - * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared - * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed) + * - PTE's use only one bit to distinguish between cacheable and uncacheable + * mappings + * - PTE's define soft_valid field to ensure there is at least one 1 bit even if + * the p bit is cleared + * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) + * and bit A (accessed) * - PTL0 has 64 entries (6 bits) * - PTL1 is not used @@ -70,4 +74,5 @@ */ +/* Macros describing number of entries in each level. */ #define PTL0_ENTRIES_ARCH 64 #define PTL1_ENTRIES_ARCH 0 @@ -75,39 +80,59 @@ #define PTL3_ENTRIES_ARCH 4096 -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +/* Macros describing size of page tables in each level. */ +#define PTL0_SIZE_ARCH ONE_FRAME +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME -#define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26) -#define PTL1_INDEX_ARCH(vaddr) 0 -#define PTL2_INDEX_ARCH(vaddr) 0 -#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>14) & 0xfff) +/* Macros calculating entry indices for each level. */ +#define PTL0_INDEX_ARCH(vaddr) ((vaddr) >> 26) +#define PTL1_INDEX_ARCH(vaddr) 0 +#define PTL2_INDEX_ARCH(vaddr) 0 +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 14) & 0xfff) +/* Set accessor for PTL0 address. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) -#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12) -#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) -#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) -#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<12) +/* Get PTE address accessors for each level. */ +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ + (((pte_t *) (ptl0))[(i)].pfn << 12) +#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ + (ptl1) +#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ + (ptl2) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ + (((pte_t *) (ptl3))[(i)].pfn << 12) -#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].pfn = (a)>>12) +/* Set PTE address accessors for each level. */ +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ + (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) -#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].pfn = (a)>>12) +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ + (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12) -#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) -#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT -#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT -#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) +/* Get PTE flags accessors for each level. */ +#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ + get_pt_flags((pte_t *) (ptl0), (index_t) (i)) +#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ + PAGE_PRESENT +#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ + PAGE_PRESENT +#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ + get_pt_flags((pte_t *) (ptl3), (index_t) (i)) -#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x)) +/* Set PTE flags accessors for each level. */ +#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ + set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) -#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) +#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ + set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) +/* Last-level info macros. */ #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) #define PTE_PRESENT_ARCH(pte) ((pte)->p != 0) -#define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn<<12) +#define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn << 12) #define PTE_WRITABLE_ARCH(pte) ((pte)->w != 0) #define PTE_EXECUTABLE_ARCH(pte) 1 @@ -122,14 +147,11 @@ pte_t *p = &pt[i]; - return ( - (p->cacheable<p)<w)<g<cacheable << PAGE_CACHEABLE_SHIFT) | + ((!p->p) << PAGE_PRESENT_SHIFT) | + (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | + ((p->w) << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | + (p->g << PAGE_GLOBAL_SHIFT)); } Index: kernel/arch/ppc32/include/mm/page.h =================================================================== --- kernel/arch/ppc32/include/mm/page.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/arch/ppc32/include/mm/page.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -33,6 +33,6 @@ */ -#ifndef __ppc32_PAGE_H__ -#define __ppc32_PAGE_H__ +#ifndef KERN_ppc32_PAGE_H_ +#define KERN_ppc32_PAGE_H_ #include @@ -66,4 +66,5 @@ */ +/* Number of entries in each level. */ #define PTL0_ENTRIES_ARCH 1024 #define PTL1_ENTRIES_ARCH 0 @@ -71,9 +72,11 @@ #define PTL3_ENTRIES_ARCH 1024 -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +/* Page table sizes for each level. */ +#define PTL0_SIZE_ARCH ONE_FRAME +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME +/* Macros calculating indices into page tables on each level. */ #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) #define PTL1_INDEX_ARCH(vaddr) 0 @@ -81,25 +84,42 @@ #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff) -#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *) (ptl0))[(i)].pfn << 12) -#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) -#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) -#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *) (ptl3))[(i)].pfn << 12) +/* Get PTE address accessors for each level. */ +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ + (((pte_t *) (ptl0))[(i)].pfn << 12) +#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ + (ptl1) +#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ + (ptl2) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ + (((pte_t *) (ptl3))[(i)].pfn << 12) +/* Set PTE address accessors for each level. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) -#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12) +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ + (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) -#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12) +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ + (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12) -#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t) (i)) -#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT -#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT -#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t) (i)) +/* Get PTE flags accessors for each level. */ +#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ + get_pt_flags((pte_t *) (ptl0), (index_t) (i)) +#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ + PAGE_PRESENT +#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ + PAGE_PRESENT +#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ + get_pt_flags((pte_t *) (ptl3), (index_t) (i)) -#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) +/* Set PTE flags accessors for each level. */ +#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ + set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) -#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) +#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ + set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) +/* Macros for querying the last-level PTEs. */ #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) #define PTE_PRESENT_ARCH(pte) ((pte)->p != 0) @@ -117,13 +137,11 @@ pte_t *p = &pt[i]; - return ( - (1 << PAGE_CACHEABLE_SHIFT) | - ((!p->p) << PAGE_PRESENT_SHIFT) | - (1 << PAGE_USER_SHIFT) | - (1 << PAGE_READ_SHIFT) | - (1 << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | - (p->g << PAGE_GLOBAL_SHIFT) - ); + return ((1 << PAGE_CACHEABLE_SHIFT) | + ((!p->p) << PAGE_PRESENT_SHIFT) | + (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | + (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | + (p->g << PAGE_GLOBAL_SHIFT)); } Index: kernel/arch/ppc64/include/mm/page.h =================================================================== --- kernel/arch/ppc64/include/mm/page.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/arch/ppc64/include/mm/page.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -66,4 +66,5 @@ */ +/* Number of entries in each level. */ #define PTL0_ENTRIES_ARCH 1024 #define PTL1_ENTRIES_ARCH 0 @@ -71,4 +72,5 @@ #define PTL3_ENTRIES_ARCH 1024 +/* Sizes of page tables in each level. */ #define PTL0_SIZE_ARCH ONE_FRAME #define PTL1_SIZE_ARCH 0 @@ -76,4 +78,5 @@ #define PTL3_SIZE_ARCH ONE_FRAME +/* Macros calculating indices into page tables in each level. */ #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) #define PTL1_INDEX_ARCH(vaddr) 0 @@ -81,25 +84,42 @@ #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff) -#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *) (ptl0))[(i)].pfn << 12) -#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) -#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) -#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *) (ptl3))[(i)].pfn << 12) +/* Get PTE address accessors for each level. */ +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ + (((pte_t *) (ptl0))[(i)].pfn << 12) +#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ + (ptl1) +#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ + (ptl2) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ + (((pte_t *) (ptl3))[(i)].pfn << 12) +/* Set PTE address accessors for each level. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) -#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12) +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ + (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) -#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12) +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ + (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12) -#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t) (i)) -#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT -#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT -#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t) (i)) +/* Get PTE flags accessors for each level. */ +#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ + get_pt_flags((pte_t *) (ptl0), (index_t) (i)) +#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ + PAGE_PRESENT +#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ + PAGE_PRESENT +#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ + get_pt_flags((pte_t *) (ptl3), (index_t) (i)) -#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) +/* Set PTE flags accessors for each level. */ +#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ + set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) -#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) +#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ + set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) +/* Macros for querying the last-level PTEs. */ #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) #define PTE_PRESENT_ARCH(pte) ((pte)->p != 0) @@ -117,13 +137,11 @@ pte_t *p = &pt[i]; - return ( - (1 << PAGE_CACHEABLE_SHIFT) | - ((!p->p) << PAGE_PRESENT_SHIFT) | - (1 << PAGE_USER_SHIFT) | - (1 << PAGE_READ_SHIFT) | - (1 << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | - (p->g << PAGE_GLOBAL_SHIFT) - ); + return ((1 << PAGE_CACHEABLE_SHIFT) | + ((!p->p) << PAGE_PRESENT_SHIFT) | + (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | + (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | + (p->g << PAGE_GLOBAL_SHIFT)); } Index: kernel/genarch/include/mm/page_ht.h =================================================================== --- kernel/genarch/include/mm/page_ht.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/genarch/include/mm/page_ht.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -51,6 +51,7 @@ #define PAGE_HT_ENTRIES_BITS 13 -#define PAGE_HT_ENTRIES (1<p != 0) Index: kernel/genarch/include/mm/page_pt.h =================================================================== --- kernel/genarch/include/mm/page_pt.h (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/genarch/include/mm/page_pt.h (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -83,6 +83,6 @@ /* - * These macros are provided to change shape of the 4-level - * tree of page tables on respective level. + * These macros are provided to change the shape of the 4-level tree of page + * tables on respective level. */ #define SET_PTL1_ADDRESS(ptl0, i, a) SET_PTL1_ADDRESS_ARCH(ptl0, i, a) @@ -107,4 +107,7 @@ #define SET_FRAME_FLAGS(ptl3, i, x) SET_FRAME_FLAGS_ARCH(ptl3, i, x) +/* + * Macros for querying the last-level PTEs. + */ #define PTE_VALID(p) PTE_VALID_ARCH((p)) #define PTE_PRESENT(p) PTE_PRESENT_ARCH((p)) @@ -119,5 +122,6 @@ extern page_mapping_operations_t pt_mapping_operations; -extern void page_mapping_insert_pt(as_t *as, uintptr_t page, uintptr_t frame, int flags); +extern void page_mapping_insert_pt(as_t *as, uintptr_t page, uintptr_t frame, + int flags); extern pte_t *page_mapping_find_pt(as_t *as, uintptr_t page); Index: kernel/generic/src/mm/backend_elf.c =================================================================== --- kernel/generic/src/mm/backend_elf.c (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/generic/src/mm/backend_elf.c (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -327,5 +327,5 @@ btree_insert(&area->sh_info->pagemap, (base + j * PAGE_SIZE) - area->base, - (void *) PTE_GET_FRAME(pte), NULL); + (void *) PTE_GET_FRAME(pte), NULL); page_table_unlock(area->as, false); Index: kernel/generic/src/syscall/syscall.c =================================================================== --- kernel/generic/src/syscall/syscall.c (revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe) +++ kernel/generic/src/syscall/syscall.c (revision 341140c181e949962d7871bd75d6e9f74ba669d1) @@ -93,6 +93,6 @@ /** Dispatch system call */ -unative_t syscall_handler(unative_t a1, unative_t a2, unative_t a3, - unative_t a4, unative_t id) +unative_t syscall_handler(unative_t a1, unative_t a2, unative_t a3, unative_t a4, + unative_t id) { unative_t rc; @@ -101,5 +101,6 @@ rc = syscall_table[id](a1, a2, a3, a4); else { - klog_printf("TASK %llu: Unknown syscall id %d",TASK->taskid,id); + klog_printf("TASK %llu: Unknown syscall id %d", TASK->taskid, + id); task_kill(TASK->taskid); thread_exit();