Changeset 3156582 in mainline for arch/mips/src/interrupt.c

Timestamp:

2005-09-11T12:48:42Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8e3fb24c

Parents:

8491c48

Message:

Updated symtab so that it works correctly with BE architectures.
Changed compiler for BE MIPS to be mips-sgi-irix5, because
mipsel -EB does not behave correctly.
Doc updates to amd64.
Added ARC BIOS support to MIPS architecture. Putchar works correctly,
kernel passed FPU & some rwlock tests.

File:

• arch/mips/src/interrupt.c (modified) (4 diffs)

arch/mips/src/interrupt.c

@@ -33 +33 @@
 #include <time/clock.h>
 #include <panic.h>
+#include <print.h>
+#include <symtab.h>
+#include <arch/drivers/arc.h>
+
+static void print_regdump(struct exception_regdump *pstate)
+{
+        char *pcsymbol = "";
+        char *rasymbol = "";
+
+        char *s = get_symtab_entry(pstate->epc);
+        if (s)
+                pcsymbol = s;
+        s = get_symtab_entry(pstate->ra);
+        if (s)
+                rasymbol = s;
+        
+        printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol,
+               pstate->ra,rasymbol);
+}
 
 pri_t cpu_priority_high(void)
@@ -58 +77 @@
 }
 
-void interrupt(void)
+void interrupt(struct exception_regdump *pstate)
 {
         __u32 cause;
@@ -70 +89 @@
                         switch (i) {
                                 case 0: /* SW0 - Software interrupt 0 */
-                                        cp0_cause_write(cause & ~(1 << 8)); /* clear SW0 interrupt */
+                                        cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
                                         break;
                                 case 1: /* SW1 - Software interrupt 1 */
-                                        cp0_cause_write(cause & ~(1 << 9)); /* clear SW1 interrupt */
+                                        cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
                                         break;
                                 case 2: /* IRQ0 */
@@ -80 +99 @@
                                 case 5: /* IRQ3 */
                                 case 6: /* IRQ4 */
+                                        print_regdump(pstate);
                                         panic("unhandled interrupt %d\n", i);
                                         break;