Changeset 3156582 in mainline for arch/amd64/src

Timestamp:

2005-09-11T12:48:42Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8e3fb24c

Parents:

8491c48

Message:

Updated symtab so that it works correctly with BE architectures.
Changed compiler for BE MIPS to be mips-sgi-irix5, because
mipsel -EB does not behave correctly.
Doc updates to amd64.
Added ARC BIOS support to MIPS architecture. Putchar works correctly,
kernel passed FPU & some rwlock tests.

Location:

arch/amd64/src

Files:

• asm_utils.S (modified) (3 diffs)
• fpu_context.c (modified) (2 diffs)
• pm.c (modified) (1 diff)

arch/amd64/src/asm_utils.S

@@ -59 +59 @@
 .global utext
 utext:
-        xor %ax,%ax;
-        mov %ax,%ds;
-        mov %ax,%es;
-        mov %ax,%fs;
-        mov %ax,%gs;
 0:
         int $48
@@ -178 +173 @@
         push_all_gpr
 
-        # trap_dispatcher(i, stack)
         movq $(\i),%rdi   # %rdi - first parameter
         movq %rbp, %rsi
         addq $8, %rsi     # %rsi - second parameter - original stack
-        call trap_dispatcher
+        call trap_dispatcher    # trap_dispatcher(i, stack)
 
 # Test if this is interrupt with error word or not
@@ -217 +211 @@
 h_start:
         handler 0 IDT_ITEMS
-#       handler 64 128  
-#       handler 128 192
-#       handler 192 256
 h_end:
         

arch/amd64/src/fpu_context.c

@@ -32 +32 @@
 #include <cpu.h>
 
+/** Save FPU (mmx, sse) context using fxsave instruction */
 void fpu_context_save(fpu_context_t *fctx)
 {
@@ -44 +45 @@
 }
 
+/** Restore FPU (mmx,sse) context using fxrstor instruction */
 void fpu_context_restore(fpu_context_t *fctx)
 {

arch/amd64/src/pm.c

@@ -92 +92 @@
           .granularity = 1, 
           .base_24_31  = 0 },
-        /* KTEXT 32-bit protected */
+        /* KTEXT 32-bit protected, for protected mode before long mode */
         { .limit_0_15  = 0xffff, 
           .base_0_15   = 0,