Changeset 2d0c3a6 in mainline for kernel

Timestamp:

2010-08-12T20:50:50Z (15 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ddd7118

Parents:

ff586e06 (diff), 527298a (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge from lp:~jsvoboda/helenos/gta02 (GTA02 touchscreen driver).

Location:

kernel

Files:

• arch/arm32/src/mach/gta02/gta02.c (modified) (1 diff)
• genarch/include/drivers/s3c24xx_uart/s3c24xx_uart.h (modified) (1 diff)
• genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c (modified) (2 diffs)

kernel/arch/arm32/src/mach/gta02/gta02.c

@@ -221 +221 @@
                 }
         }
+
+        /* Enable interrupts from ADC */
+        s3c24xx_irqc_src_enable(&gta02_irqc, S3C24XX_INT_ADC);
+
+        /* Enable interrupts from ADC sub-sources */
+        s3c24xx_irqc_subsrc_enable(&gta02_irqc, S3C24XX_SUBINT_ADC_S);
+        s3c24xx_irqc_subsrc_enable(&gta02_irqc, S3C24XX_SUBINT_TC);
 }
 

kernel/genarch/include/drivers/s3c24xx_uart/s3c24xx_uart.h

@@ -60 +60 @@
 } s3c24xx_uart_io_t;
 
+/* Bits in UTRSTAT register */
+#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
+#define S3C24XX_UTRSTAT_RDATA           0x1
+
+/* Bits in UFSTAT register */
+#define S3C24XX_UFSTAT_TX_FULL          0x4000
+#define S3C24XX_UFSTAT_RX_FULL          0x0040
+#define S3C24XX_UFSTAT_RX_COUNT         0x002f
+
+/* Bits in UCON register */
+#define UCON_RX_INT_LEVEL               0x100
+
+/* Bits in UFCON register */
+#define UFCON_TX_FIFO_TLEVEL_EMPTY      0x00
+#define UFCON_RX_FIFO_TLEVEL_1B         0x00
+#define UFCON_FIFO_ENABLE               0x01
+
+
 /** S3C24xx UART instance */
 typedef struct {

kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c

@@ -46 +46 @@
 #include <sysinfo/sysinfo.h>
 #include <str.h>
-
-/* Bits in UTRSTAT register */
-#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
-#define S3C24XX_UTRSTAT_RDATA           0x1
-
-#define S3C24XX_UFSTAT_TX_FULL          0x4000
-#define S3C24XX_UFSTAT_RX_FULL          0x0040
-#define S3C24XX_UFSTAT_RX_COUNT         0x002f
 
 static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
@@ -129 +121 @@
 
         /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
-        pio_write_32(&uart->io->ufcon, 0x01);
+        pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
+            UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
 
         /* Set RX interrupt to pulse mode */
         pio_write_32(&uart->io->ucon,
-            pio_read_32(&uart->io->ucon) & ~(1 << 8));
+            pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
 
         if (!fb_exported) {