Changeset 2bcf6c6 in mainline for kernel/arch/amd64

Timestamp:

2012-07-27T13:34:48Z (13 years ago)

Author:

Adam Hraska <adam.hraska+hos@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4ec9ea41

Parents:

3bb732b

Message:

Added atomic_cas_ptr() including a sanity test for ia32 and amd64.

File:

• kernel/arch/amd64/include/atomic.h (modified) (1 diff)

kernel/arch/amd64/include/atomic.h

@@ -140 +140 @@
 }
 
+
+#define _atomic_cas_ptr_impl(pptr, exp_val, new_val, old_val, prefix)
+        asm volatile ( \
+                prefix " cmpxchgq %[newval], %[ptr]\n" \
+                : /* Output operands. */ \
+                /* Old/current value is returned in eax. */ \
+                [oldval] "=a" (old_val), \
+                /* (*ptr) will be read and written to, hence "+" */ \
+                [ptr] "+m" (*pptr) \
+                : /* Input operands. */ \
+                /* Expected value must be in eax. */ \
+                [expval] "a" (exp_val), \
+                /* The new value may be in any register. */ \
+                [newval] "r" (new_val) \
+                : "memory" \
+        )
+        
+/** Atomically compares and swaps the pointer at pptr. */
+NO_TRACE static inline void * atomic_cas_ptr(void **pptr, 
+        void *exp_val, void *new_val)
+{
+        void *old_val;
+        _atomic_cas_ptr_impl(pptr, exp_val, new_val, old_val, "lock\n");
+        return old_val;
+}
+
+/** Compare-and-swap of a pointer that is atomic wrt to local cpu's interrupts.
+ * 
+ * This function is NOT smp safe and is not atomic with respect to other cpus.
+ */
+NO_TRACE static inline void * atomic_cas_ptr_local(void **pptr, 
+        void *exp_val, void *new_val)
+{
+        void *old_val;
+        _atomic_cas_ptr_impl(pptr, exp_val, new_val, old_val, "");
+        return old_val;
+}
+
+#undef _atomic_cas_ptr_impl
+
+
 #endif