Changeset 2b95d13 in mainline for boot/arch


Ignore:
Timestamp:
2013-03-12T21:07:15Z (13 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
606f6a1
Parents:
976c434 (diff), eceff5f (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
boot/arch/arm32
Files:
9 edited

Legend:

Unmodified
Added
Removed

  • boot/arch/arm32/Makefile.inc

    r976c434 r2b95d13  
    3535endif
    3636
    37 ifeq ($(MACHINE), beagleboardxm)
     37ifeq ($(MACHINE), $(filter $(MACHINE),beagleboardxm beaglebone))
    3838        BOOT_OUTPUT = image.boot
    3939        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
    … …  
    4949BITS = 32
    5050ENDIANESS = LE
    51 EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
     51EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
    5252
    5353ifeq ($(MACHINE), gta02)
    5454RD_SRVS_ESSENTIAL += \
    5555        $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
    56         $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
     56        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
    5757endif
    5858
    5959RD_DRVS += \
    6060        infrastructure/rootamdm37x \
     61        fb/amdm37x_dispc \
    6162        bus/usb/ehci \
    6263        bus/usb/ohci \

  • boot/arch/arm32/_link.ld.in

    r976c434 r2b95d13  
    1111        . = BOOT_BASE + 0x8000;
    1212        .data : {
     13                bdata_start = .;
    1314                *(BOOTPT);      /* bootstrap page table */
    1415                *(BOOTSTACK);   /* bootstrap stack */
    … …  
    2425[[COMPONENTS]]
    2526        }
    26        
     27        bdata_end = .;
     28
    2729        /DISCARD/ : {
    2830                *(.gnu.*);

  • boot/arch/arm32/include/arch.h

    r976c434 r2b95d13  
    4444#elif defined MACHINE_beagleboardxm
    4545#define BOOT_BASE       0x80000000
     46#elif defined MACHINE_beaglebone
     47#define BOOT_BASE       0x80000000
    4648#else
    4749#define BOOT_BASE       0x00000000
    … …  
    5153
    5254#ifdef MACHINE_beagleboardxm
     55        #define PA_OFFSET 0
     56#elif defined MACHINE_beaglebone
    5357        #define PA_OFFSET 0
    5458#else

  • boot/arch/arm32/include/main.h

    r976c434 r2b95d13  
    5151#define BBXM_THR_FULL           0x00000001
    5252
     53/** Beaglebone UART register addresses
     54 *
     55 * This is UART0 of AM335x CPU
     56 */
     57#define BBONE_SCONS_THR         0x44E09000
     58#define BBONE_SCONS_SSR         0x44E09044
     59
     60/** Check this bit before writing (tx fifo full) */
     61#define BBONE_TXFIFO_FULL       0x00000001
    5362
    5463/** GTA02 serial console UART register addresses.

  • boot/arch/arm32/include/mm.h

    r976c434 r2b95d13  
    4747/** Describe "section" page table entry (one-level paging with 1 MB sized pages). */
    4848#define PTE_DESCRIPTOR_SECTION  0x02
     49/** Shift of memory address in section descriptor */
     50#define PTE_SECTION_SHIFT  20
    4951
    5052/** Page table access rights: user - no access, kernel - read/write. */
    5153#define PTE_AP_USER_NO_KERNEL_RW  0x01
     54
     55/** Start of memory mapped I/O area for GTA02 */
     56#define GTA02_IOMEM_START  0x48000000
     57/** End of memory mapped I/O area for GTA02 */
     58#define GTA02_IOMEM_END  0x60000000
     59
     60/** Start of ram memory on BBxM */
     61#define BBXM_RAM_START   0x80000000
     62/** Start of ram memory on BBxM */
     63#define BBXM_RAM_END   0xc0000000
     64
     65/** Start of ram memory on AM335x */
     66#define AM335x_RAM_START   0x80000000
     67/** End of ram memory on AM335x */
     68#define AM335x_RAM_END     0xC0000000
     69
    5270
    5371/* Page table level 0 entry - "section" format is used
    … …  
    6381        unsigned int access_permission_0 : 2;
    6482        unsigned int tex : 3;
    65         unsigned int access_permission_1 : 2;
     83        unsigned int access_permission_1 : 1;
     84        unsigned int shareable : 1;
    6685        unsigned int non_global : 1;
    6786        unsigned int should_be_zero_2 : 1;

  • boot/arch/arm32/src/asm.S

    r976c434 r2b95d13  
    6060        # before passing control to the copied code.
    6161        #
     62
     63        #
     64        # r0 is kernel entry point
     65        # r1 is pointer to the bootinfo structure
     66
     67#define CP15_C1_IC              12
     68#define CP15_C1_BP              11
     69#define CP15_C1_DC              2
     70        # Disable I-cache and D-cache before the kernel is started.
     71        mrc     p15, 0, r4, c1, c0, 0
     72        bic     r4, r4, #(1 << CP15_C1_DC)
     73        bic     r4, r4, #(1 << CP15_C1_IC)
     74        bic     r4, r4, #(1 << CP15_C1_BP)
     75        mcr     p15, 0, r4, c1, c0, 0
     76
     77       
     78        #Wait for the operations to complete
     79#ifdef PROCESSOR_ARCH_armv7_a
     80        dsb
     81#else
     82        #cp15 dsb, r4 is ignored (should be zero)
     83        mcr p15, 0, r4, c7, c10, 4
     84#endif
     85       
     86        # Clean ICache and BPredictors, r4 ignored (SBZ)
     87        mcr p15, 0, r4, c7, c5, 0
     88        nop
     89
     90        #Wait for the operations to complete
     91#ifdef PROCESSOR_ARCH_armv7_a
     92        isb
     93        nop
     94#else
     95        # cp15 isb
     96        mcr p15, 0, r4, c7, c5, 4
     97        nop
     98#endif
    6299        mov pc, r0

  • boot/arch/arm32/src/main.c

    r976c434 r2b95d13  
    5050#define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
    5151
     52extern void *bdata_start;
     53extern void *bdata_end;
     54
     55
     56static inline void invalidate_icache(void)
     57{
     58        /* ICIALLU Invalidate entire ICache */
     59        asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
     60}
     61
     62static inline void invalidate_dcache(void *address, size_t size)
     63{
     64        const uintptr_t addr = (uintptr_t)address;
     65        /* DCIMVAC - invalidate by address to the point of coherence */
     66        for (uintptr_t a = addr; a < addr + size; a += 4) {
     67                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
     68        }
     69}
     70
     71static inline void clean_dcache_poc(void *address, size_t size)
     72{
     73        const uintptr_t addr = (uintptr_t)address;
     74        /* DCCMVAC - clean by address to the point of coherence */
     75        for (uintptr_t a = addr; a < addr + size; a += 4) {
     76                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
     77        }
     78}
     79
    5280static bootinfo_t bootinfo;
    5381
    5482void bootstrap(void)
    5583{
     84        /* Make sure  we run in memory code when caches are enabled,
     85         * make sure we read memory data too. This part is ARMv7 specific as
     86         * ARMv7 no longer invalidates caches on restart.
     87         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
     88        invalidate_icache();
     89        invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
     90
     91        /* Enable MMU and caches */
    5692        mmu_start();
    5793        version_print();
    5894       
     95        printf("Boot data: %p -> %p\n", &bdata_start, &bdata_end);
    5996        printf("\nMemory statistics\n");
    6097        printf(" %p|%p: bootstrap stack\n", &boot_stack, &boot_stack);
    … …  
    64101            (void *) PA2KA(BOOT_OFFSET), (void *) BOOT_OFFSET);
    65102       
    66         size_t i;
    67         for (i = 0; i < COMPONENTS; i++)
     103        for (size_t i = 0; i < COMPONENTS; i++) {
    68104                printf(" %p|%p: %s image (%u/%u bytes)\n", components[i].start,
    69105                    components[i].start, components[i].name, components[i].inflated,
    70106                    components[i].size);
     107                invalidate_dcache(components[i].start, components[i].size);
     108        }
    71109       
    72110        void *dest[COMPONENTS];
    … …  
    74112        size_t cnt = 0;
    75113        bootinfo.cnt = 0;
    76         for (i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
     114        for (size_t i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
    77115                top = ALIGN_UP(top, PAGE_SIZE);
    78116               
    … …  
    94132        printf("\nInflating components ... ");
    95133       
    96         for (i = cnt; i > 0; i--) {
     134        for (size_t i = cnt; i > 0; i--) {
    97135                void *tail = components[i - 1].start + components[i - 1].size;
    98136                if (tail >= dest[i - 1]) {
    … …  
    106144                int err = inflate(components[i - 1].start, components[i - 1].size,
    107145                    dest[i - 1], components[i - 1].inflated);
    108                
    109146                if (err != EOK) {
    110147                        printf("\n%s: Inflating error %d\n", components[i - 1].name, err);
    111148                        halt();
    112149                }
     150                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
    113151        }
    114152       
    115153        printf(".\n");
    116154       
    117         printf("Booting the kernel... \n");
     155        printf("Booting the kernel...\n");
    118156        jump_to_kernel((void *) PA2KA(BOOT_OFFSET), &bootinfo);
    119157}

  • boot/arch/arm32/src/mm.c

    r976c434 r2b95d13  
    3838#include <arch/mm.h>
    3939
     40/** Disable the MMU */
     41static void disable_paging(void)
     42{
     43        asm volatile (
     44                "mrc p15, 0, r0, c1, c0, 0\n"
     45                "bic r0, r0, #1\n"
     46                "mcr p15, 0, r0, c1, c0, 0\n"
     47                ::: "r0"
     48        );
     49}
     50
     51/** Check if caching can be enabled for a given memory section.
     52 *
     53 * Memory areas used for I/O are excluded from caching.
     54 * At the moment caching is enabled only on GTA02.
     55 *
     56 * @param section       The section number.
     57 *
     58 * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
     59*/
     60static inline int section_cacheable(pfn_t section)
     61{
     62#ifdef MACHINE_gta02
     63        unsigned long address = section << PTE_SECTION_SHIFT;
     64
     65        if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
     66                return 0;
     67        else
     68                return 1;
     69#elif defined MACHINE_beagleboardxm
     70        const unsigned long address = section << PTE_SECTION_SHIFT;
     71        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
     72                return 1;
     73#elif defined MACHINE_beaglebone
     74        const unsigned long address = section << PTE_SECTION_SHIFT;
     75        if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
     76                return 1;
     77#endif
     78        return 0;
     79}
     80
    4081/** Initialize "section" page table entry.
    4182 *
    … …  
    5596        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    5697        pte->bufferable = 1;
    57         pte->cacheable = 0;
     98        pte->cacheable = section_cacheable(frame);
    5899        pte->xn = 0;
    59100        pte->domain = 0;
    … …  
    62103        pte->tex = 0;
    63104        pte->access_permission_1 = 0;
     105        pte->shareable = 0;
    64106        pte->non_global = 0;
    65107        pte->should_be_zero_2 = 0;
    … …  
    76118        for (page = 0; page < split_page; page++)
    77119                init_ptl0_section(&boot_pt[page], page);
    78        
    79         /*
    80          * Create 1:1 virtual-physical mapping in kernel space
    81          * (upper 2 GB), physical addresses start from 0.
    82          */
    83         /* BeagleBoard-xM (DM37x) memory starts at 2GB border,
    84          * thus mapping only lower 2GB is not not enough.
    85          * Map entire AS 1:1 instead and hope it works. */
    86         for (page = split_page; page < PTL0_ENTRIES; page++)
    87 #ifndef MACHINE_beagleboardxm
    88                 init_ptl0_section(&boot_pt[page], page - split_page);
    89 #else
    90                 init_ptl0_section(&boot_pt[page], page);
    91 #endif
    92120       
    93121        asm volatile (
    … …  
    106134                "ldr r0, =0x55555555\n"
    107135                "mcr p15, 0, r0, c3, c0, 0\n"
    108                
    109 #ifdef PROCESSOR_armv7_a
    110                 /* Read Auxiliary control register */
    111                 "mrc p15, 0, r0, c1, c0, 1\n"
    112                 /* Mask to enable L2 cache */
    113                 "ldr r1, =0x00000002\n"
    114                 "orr r0, r0, r1\n"
    115                 /* Store Auxiliary control register */
    116                 "mrc p15, 0, r0, c1, c0, 1\n"
    117 #endif
     136
    118137                /* Current settings */
    119138                "mrc p15, 0, r0, c1, c0, 0\n"
    120139               
    121 #ifdef PROCESSOR_armv7_a
    122                 /* Mask to enable paging, caching */
    123                 "ldr r1, =0x00000005\n"
    124 #else
    125                 /* Mask to enable paging */
    126                 "ldr r1, =0x00000001\n"
    127 #endif
     140                /* Enable ICache, DCache, BPredictors and MMU,
     141                 * we disable caches before jumping to kernel
     142                 * so this is safe for all archs.
     143                 */
     144                "ldr r1, =0x00001805\n"
     145               
    128146                "orr r0, r0, r1\n"
     147
     148                /* Invalidate the TLB content before turning on the MMU.
     149                 * ARMv7-A Reference manual, B3.10.3
     150                 */
     151                "mcr p15, 0, r0, c8, c7, 0\n"
    129152               
    130                 /* Store settings */
     153                /* Store settings, enable the MMU */
    131154                "mcr p15, 0, r0, c1, c0, 0\n"
    132155                ::: "r0", "r1"
    … …  
    136159/** Start the MMU - initialize page table and enable paging. */
    137160void mmu_start() {
     161        disable_paging();
    138162        init_boot_pt();
    139163        enable_paging();

  • boot/arch/arm32/src/putchar.c

    r976c434 r2b95d13  
    4040#include <putchar.h>
    4141#include <str.h>
     42
     43#ifdef MACHINE_beaglebone
     44
     45/** Send a byte to the am335x serial console.
     46 *
     47 * @param byte          Byte to send.
     48 */
     49static void scons_sendb_bbone(uint8_t byte)
     50{
     51        volatile uint32_t *thr =
     52                (volatile uint32_t *) BBONE_SCONS_THR;
     53        volatile uint32_t *ssr =
     54                (volatile uint32_t *) BBONE_SCONS_SSR;
     55
     56        /* Wait until transmitter is empty */
     57        while (*ssr & BBONE_TXFIFO_FULL);
     58
     59        /* Transmit byte */
     60        *thr = (uint32_t) byte;
     61}
     62
     63#endif
    4264
    4365#ifdef MACHINE_beagleboardxm
    … …  
    106128static void scons_sendb(uint8_t byte)
    107129{
     130#ifdef MACHINE_beaglebone
     131        scons_sendb_bbone(byte);
     132#endif
    108133#ifdef MACHINE_beagleboardxm
    109134        scons_sendb_bbxm(byte);
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