Changeset 29b2bbf in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2006-09-18T22:10:20Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
19dba2b
Parents:
57da95c
Message:

sparc64 work:

  • Experimental support for TSB (Translation Storage Buffer).
Location:
kernel/arch/sparc64/include
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/arch.h

    r57da95c r29b2bbf  
    3838#define KERN_sparc64_ARCH_H_
    3939
    40 #define ASI_AIUP        0x10    /** Access to primary context with user privileges. */
    41 #define ASI_AIUS        0x11    /** Access to secondary context with user privileges. */
     40#define ASI_AIUP        0x10            /** Access to primary context with user privileges. */
     41#define ASI_AIUS        0x11            /** Access to secondary context with user privileges. */
    4242
    43 #define NWINDOW         8       /** Number of register window sets. */
     43#define ASI_NUCLEUS_QUAD_LDD    0x24    /** ASI for 16-byte atomic loads. */
     44
     45#define NWINDOW         8               /** Number of register window sets. */
    4446
    4547#endif

  • kernel/arch/sparc64/include/barrier.h

    r57da95c r29b2bbf  
    4242#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    4343
    44 #define memory_barrier()
    45 #define read_barrier()
    46 #define write_barrier()
     44#define memory_barrier()        __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
     45#define read_barrier()          __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
     46#define write_barrier()         __asm__ volatile ("membar #StoreStore\n" ::: "memory")
    4747
    4848/** Flush Instruction Memory instruction. */

  • kernel/arch/sparc64/include/mm/mmu.h

    r57da95c r29b2bbf  
    4949
    5050/* Virtual Addresses within ASI_IMMU. */
    51 #define VA_IMMU_TAG_TARGET              0x0     /**< IMMU tag target register. */
     51#define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
    5252#define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
    5353#define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
    … …  
    6565
    6666/* Virtual Addresses within ASI_DMMU. */
    67 #define VA_DMMU_TAG_TARGET              0x0     /**< DMMU tag target register. */
     67#define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
    6868#define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
    6969#define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */

  • kernel/arch/sparc64/include/mm/tsb.h

    r57da95c r29b2bbf  
    3636#define KERN_sparc64_TSB_H_
    3737
    38 #include <arch/mm/tte.h>
    39 #include <arch/mm/mmu.h>
    40 #include <arch/types.h>
    41 #include <typedefs.h>
    42 
    4338/*
    4439 * ITSB abd DTSB will claim 64K of memory, which
    … …  
    5247#define DTSB_ENTRY_COUNT                (512*(1<<TSB_SIZE))
    5348
     49#define TSB_TAG_TARGET_CONTEXT_SHIFT    48
     50
     51#ifndef __ASM__
     52
     53#include <arch/mm/tte.h>
     54#include <arch/mm/mmu.h>
     55#include <arch/types.h>
     56#include <typedefs.h>
     57
     58/** TSB Tag Target register. */
     59union tsb_tag_target {
     60        uint64_t value;
     61        struct {
     62                unsigned invalid : 1;   /**< Invalidated by software. */
     63                unsigned : 2;
     64                unsigned context : 13;  /**< Software ASID. */
     65                unsigned : 6;
     66                uint64_t va_tag : 42;   /**< Virtual address bits <63:22>. */
     67        } __attribute__ ((packed));
     68};
     69typedef union tsb_tag_target tsb_tag_target_t;
     70
     71/** TSB entry. */
    5472struct tsb_entry {
    55         tte_tag_t tag;
     73        tsb_tag_target_t tag;
    5674        tte_data_t data;
    5775} __attribute__ ((packed));
    … …  
    110128
    111129extern void tsb_invalidate(as_t *as, uintptr_t page, count_t pages);
     130extern void itsb_pte_copy(pte_t *t);
     131extern void dtsb_pte_copy(pte_t *t, bool ro);
     132
     133#endif /* !def __ASM__ */
    112134
    113135#endif

  • kernel/arch/sparc64/include/mm/tte.h

    r57da95c r29b2bbf  
    5151#include <arch/types.h>
    5252
     53#define VA_TAG_PAGE_SHIFT       22
     54
    5355/** Translation Table Entry - Tag. */
    5456union tte_tag {

  • kernel/arch/sparc64/include/trap/mmu.h

    r57da95c r29b2bbf  
    4545#include <arch/trap/regwin.h>
    4646
     47#ifdef CONFIG_TSB
     48#include <arch/mm/tsb.h>
     49#endif
     50
    4751#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS     0x64
    4852#define TT_FAST_DATA_ACCESS_MMU_MISS            0x68
    … …  
    5761         * First, try to refill TLB from TSB.
    5862         */
    59         ! TODO
    6063
     64#ifdef CONFIG_TSB
     65        ldxa [%g0] ASI_IMMU, %g1                        ! read TSB Tag Target Register
     66        ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2        ! read TSB 8K Pointer
     67        ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
     68        cmp %g1, %g4                                    ! is this the entry we are looking for?
     69        bne,pn %xcc, 0f
     70        nop
     71        stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG            ! copy mapping from ITSB to ITLB
     72        retry
     73#endif
     74
     750:
    6176        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    6277        PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
    … …  
    6782         * First, try to refill TLB from TSB.
    6883         */
    69         ! TODO
     84
     85#ifdef CONFIG_TSB
     86        ldxa [%g0] ASI_DMMU, %g1                        ! read TSB Tag Target Register
     87        srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2     ! is this kernel miss?
     88        brz,pn %g2, 0f
     89        ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3        ! read TSB 8K Pointer
     90        ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
     91        cmp %g1, %g4                                    ! is this the entry we are looking for?
     92        bne,pn %xcc, 0f
     93        nop
     94        stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG            ! copy mapping from DTSB to DTLB
     95        retry
     96#endif
    7097
    7198        /*
    … …  
    77104         * Note that branch-delay slots are used in order to save space.
    78105         */
    79 
     1060:
    80107        mov VA_DMMU_TAG_ACCESS, %g1
    81108        ldxa [%g1] ASI_DMMU, %g1                        ! read the faulting Context and VPN
    … …  
    111138.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
    112139        /*
    113          * First, try to refill TLB from TSB.
    114          */
    115         ! TODO
    116 
    117         /*
    118140         * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
    119141         */
     142
    120143.if (\tl > 0)
    121144        wrpr %g0, 1, %tl
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