Changeset 281b607 in mainline for arch/ia32

Timestamp:

2006-03-23T10:29:39Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a0bb10ef

Parents:

9aa72b4

Message:

Added basic kernel infrastructure for ThreadLocalStorage(TLS) for
ia32(complete),amd64(complete),mips32(missing emulation of rdhwr instruction).

Location:

arch/ia32

Files:

• include/pm.h (modified) (3 diffs)
• include/thread.h (modified) (1 diff)
• src/ia32.c (modified) (2 diffs)
• src/pm.c (modified) (3 diffs)
• src/proc/scheduler.c (modified) (2 diffs)
• src/userspace.c (modified) (2 diffs)

arch/ia32/include/pm.h

@@ -31 +31 @@
 
 #define IDT_ITEMS 64
-#define GDT_ITEMS 6
+#define GDT_ITEMS 7
 
 #define NULL_DES        0
@@ -39 +39 @@
 #define UDATA_DES       4
 #define TSS_DES         5
+#define TLS_DES         6 /* Pointer to Thread-Local-Storage data */
 
 #define selector(des)   ((des)<<3)
@@ -147 +148 @@
 
 extern void tss_initialize(struct tss *t);
+extern void set_tls_desc(__address tls);
 
 #endif /* __ASM__ */

arch/ia32/include/thread.h

@@ -30 +30 @@
 #define __ia32_THREAD_H__
 
-#define ARCH_THREAD_DATA
+#define ARCH_THREAD_DATA __native tls;
 
 #endif

arch/ia32/src/ia32.c

@@ -52 +52 @@
 #include <interrupt.h>
 #include <arch/debugger.h>
+#include <proc/thread.h>
+#include <syscall/syscall.h>
 
 void arch_pre_mm_init(void)
@@ -107 +109 @@
         }
 }
+
+/** Set Thread-local-storeage pointer
+ *
+ * TLS pointer is set in FS register. Unfortunately the 64-bit
+ * part can be set only in CPL0 mode.
+ *
+ * The specs says, that on %fs:0 there is stored contents of %fs register,
+ * we need not to go to CPL0 to read it.
+ */
+__native sys_tls_set(__native addr)
+{
+        THREAD->tls = addr;
+        set_tls_desc(addr);
+
+        return 0;
+}

arch/ia32/src/pm.c

@@ -49 +49 @@
  * mode, we use, for each privilege level, two segments spanning the
  * whole memory. One is for code and one is for data.
+ *
+ * One is for GS register which holds pointer to the TLS thread
+ * structure in it's base.
  */
 struct descriptor gdt[GDT_ITEMS] = {
@@ -62 +65 @@
         { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
         /* TSS descriptor - set up will be completed later */
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }
 };
 
@@ -215 +219 @@
         clean_AM_flag();          /* Disable alignment check */
 }
+
+void set_tls_desc(__address tls)
+{
+        struct ptr_16_32 cpugdtr;
+        struct descriptor *gdt_p = (struct descriptor *) cpugdtr.base;
+
+        __asm__ volatile ("sgdt %0\n" : : "m" (cpugdtr));
+
+        gdt_setbase(&gdt_p[TLS_DES], tls);
+        /* Reload gdt register to update GS in CPU */
+        __asm__ volatile ("lgdt %0\n" : : "m" (cpugdtr));
+}

arch/ia32/src/proc/scheduler.c

@@ -33 +33 @@
 #include <arch/context.h>       /* SP_DELTA */
 #include <arch/debugger.h>
+#include <arch/pm.h>
 
 void before_thread_runs_arch(void)
@@ -38 +39 @@
         CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
         CPU->arch.tss->ss0 = selector(KDATA_DES);
+
+        /* Set up TLS in GS register */
+        set_tls_desc(THREAD->tls);
 
 #ifdef CONFIG_DEBUG_AS_WATCHPOINT

arch/ia32/src/userspace.c

@@ -56 +56 @@
                 "popfl\n"
 
+                /* Set up GS register (TLS) */
+                "movl %6, %%gs\n"
+
                 "pushl %0\n"
                 "pushl %1\n"
@@ -66 +69 @@
                 : "i" (selector(UDATA_DES) | PL_USER), "r" (kernel_uarg->uspace_stack+THREAD_STACK_SIZE),
                   "r" (ipl), "i" (selector(UTEXT_DES) | PL_USER), "r" (kernel_uarg->uspace_entry),
-                  "r" (kernel_uarg->uspace_uarg)
+                "r" (kernel_uarg->uspace_uarg),
+                "r" (selector(TLS_DES))
                 : "eax");