Index: kernel/arch/arm32/include/cp15.h
===================================================================
--- kernel/arch/arm32/include/cp15.h	(revision a03b6090c276837d109f6591138b561bc5714cd5)
+++ kernel/arch/arm32/include/cp15.h	(revision 26e3db27f53f73210ac71afbbc7d79b24342a1c4)
@@ -55,4 +55,16 @@
 
 /* Identification registers */
+enum {
+	MIDR_IMPLEMENTER_MASK = 0xff,
+	MIDR_IMPLEMENTER_SHIFT = 24,
+	MIDR_VARIANT_MASK = 0xf,
+	MIDR_VARIANT_SHIFT = 20,
+	MIDR_ARCHITECTURE_MASK = 0xf,
+	MIDR_ARCHITECTURE_SHIFT = 16,
+	MIDR_PART_NUMBER_MASK = 0xfff,
+	MIDR_PART_NUMBER_SHIFT = 4,
+	MIDR_REVISION_MASK = 0xf,
+	MIDR_REVISION_SHIFT = 0,
+};
 CONTROL_REG_GEN_READ(MIDR, c0, 0, c0, 0);
 CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision a03b6090c276837d109f6591138b561bc5714cd5)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 26e3db27f53f73210ac71afbbc7d79b24342a1c4)
@@ -99,15 +99,12 @@
 static void arch_cpu_identify(cpu_arch_t *cpu)
 {
-	uint32_t ident;
-	asm volatile (
-		"mrc p15, 0, %[ident], c0, c0, 0\n"
-		: [ident] "=r" (ident)
-	);
-	
-	cpu->imp_num = ident >> 24;
-	cpu->variant_num = (ident << 8) >> 28;
-	cpu->arch_num = (ident << 12) >> 28;
-	cpu->prim_part_num = (ident << 16) >> 20;
-	cpu->rev_num = (ident << 28) >> 28;
+	const uint32_t ident = MIDR_read();
+
+	cpu->imp_num = (ident >> MIDR_IMPLEMENTER_SHIFT) & MIDR_IMPLEMENTER_MASK;
+	cpu->variant_num = (ident >> MIDR_VARIANT_SHIFT) & MIDR_VARIANT_MASK;
+	cpu->arch_num = (ident >> MIDR_ARCHITECTURE_SHIFT) & MIDR_ARCHITECTURE_MASK;
+	cpu->prim_part_num = (ident >> MIDR_PART_NUMBER_SHIFT) & MIDR_PART_NUMBER_MASK;
+	cpu->rev_num = (ident >> MIDR_REVISION_SHIFT) & MIDR_REVISION_MASK;
+
 	// TODO CPUs with arch_num == 0xf use CPUID scheme for identification
 	cpu->dcache_levels = dcache_levels();