Changeset 20a9b85 in mainline for pci/libpci/header.h
- Timestamp:
- 2006-05-09T10:55:02Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 46ec2c06
- Parents:
- 4a7c273
- File:
-
- 1 edited
-
pci/libpci/header.h (modified) (19 diffs)
Legend:
- Unmodified
- Added
- Removed
-
pci/libpci/header.h
r4a7c273 r20a9b85 34 34 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 35 35 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 36 #define PCI_STATUS_DEVSEL_FAST 0x000 36 #define PCI_STATUS_DEVSEL_FAST 0x000 37 37 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 38 38 #define PCI_STATUS_DEVSEL_SLOW 0x400 39 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 40 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 41 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 42 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 43 #define PCI_STATUS_DETECTED_PARITY 0x8000 39 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 40 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 41 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 42 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 43 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 44 44 45 45 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 46 46 revision */ 47 #define PCI_REVISION_ID 0x08 48 #define PCI_CLASS_PROG 0x09 49 #define PCI_CLASS_DEVICE 0x0a 47 #define PCI_REVISION_ID 0x08 /* Revision ID */ 48 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 49 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 50 50 51 51 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ … … 88 88 #define PCI_CARDBUS_CIS 0x28 89 89 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 90 #define PCI_SUBSYSTEM_ID 0x2e 90 #define PCI_SUBSYSTEM_ID 0x2e 91 91 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 92 92 #define PCI_ROM_ADDRESS_ENABLE 0x01 … … 136 136 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 137 137 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 138 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 138 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 139 139 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 140 140 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ … … 186 186 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 187 187 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 188 #define PCI_CAP_ID_PCIX 0x07 189 #define PCI_CAP_ID_HT 0x08 188 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 189 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 190 190 #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ 191 191 #define PCI_CAP_ID_DBG 0x0A /* Debug port */ … … 250 250 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */ 251 251 #define PCI_AGP_COMMAND 8 /* Control register */ 252 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 252 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 253 253 #define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ 254 254 #define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */ … … 256 256 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 257 257 #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */ 258 #define PCI_AGP_COMMAND_64BIT 0x0020 259 #define PCI_AGP_COMMAND_FW 0x0010 258 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */ 259 #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ 260 260 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ 261 261 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ … … 284 284 285 285 /* PCI-X */ 286 #define PCI_PCIX_COMMAND 2 287 #define PCI_PCIX_COMMAND_DPERE 0x0001 288 #define PCI_PCIX_COMMAND_ERO 0x0002 289 #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c 290 #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 286 #define PCI_PCIX_COMMAND 2 /* Command register offset */ 287 #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ 288 #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 289 #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ 290 #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 291 291 #define PCI_PCIX_COMMAND_RESERVED 0xf80 292 #define PCI_PCIX_STATUS 4 292 #define PCI_PCIX_STATUS 4 /* Status register offset */ 293 293 #define PCI_PCIX_STATUS_FUNCTION 0x00000007 294 294 #define PCI_PCIX_STATUS_DEVICE 0x000000f8 … … 296 296 #define PCI_PCIX_STATUS_64BIT 0x00010000 297 297 #define PCI_PCIX_STATUS_133MHZ 0x00020000 298 #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 299 #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 300 #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 301 #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 298 #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ 299 #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ 300 #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ 301 #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ 302 302 #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 303 303 #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 304 #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 305 #define PCI_PCIX_STATUS_266MHZ 0x40000000 306 #define PCI_PCIX_STATUS_533MHZ 0x80000000 304 #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ 305 #define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 306 #define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 307 307 #define PCI_PCIX_SIZEOF 4 308 308 309 309 /* PCI-X Bridges */ 310 #define PCI_PCIX_BRIDGE_SEC_STATUS 2 310 #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ 311 311 #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 312 312 #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 313 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 314 #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 315 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 313 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ 314 #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ 315 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ 316 316 #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 317 317 #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 318 318 #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 319 #define PCI_PCIX_BRIDGE_STATUS 4 319 #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ 320 320 #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 321 321 #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 … … 323 323 #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 324 324 #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 325 #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 326 #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 327 #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 325 #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ 326 #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ 327 #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ 328 328 #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 329 329 #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 330 #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 331 #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 330 #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ 331 #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ 332 332 #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff 333 333 #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 … … 502 502 #define PCI_HT_SW_PMASK 4 /* Partition Mask Register */ 503 503 #define PCI_HT_SW_SWINF 8 /* Switch Info Register */ 504 #define PCI_HT_SW_SWINF_DP 0x0000001f 505 #define PCI_HT_SW_SWINF_EN 0x00000020 506 #define PCI_HT_SW_SWINF_CR 0x00000040 507 #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 508 #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 509 #define PCI_HT_SW_SWINF_SBIDX 0x00002000 510 #define PCI_HT_SW_SWINF_HP 0x00040000 511 #define PCI_HT_SW_SWINF_HIDE 0x00080000 504 #define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */ 505 #define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */ 506 #define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */ 507 #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */ 508 #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */ 509 #define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */ 510 #define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */ 511 #define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */ 512 512 #define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */ 513 513 #define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */ … … 546 546 /* Register indices */ 547 547 #define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */ 548 #define PCI_HT_IDC_LINT 0x00ff0000 548 #define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */ 549 549 #define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */ 550 550 /* Low part (at index) */ 551 #define PCI_HT_IDC_IDR_MASK 0x10000001 552 #define PCI_HT_IDC_IDR_POL 0x10000002 553 #define PCI_HT_IDC_IDR_II_2 0x1000001c 554 #define PCI_HT_IDC_IDR_II_5 0x10000020 555 #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 556 #define PCI_HT_IDC_IDR_II_24 0xff000000 551 #define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */ 552 #define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */ 553 #define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */ 554 #define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */ 555 #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */ 556 #define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */ 557 557 /* High part (at index + 1) */ 558 #define PCI_HT_IDC_IDR_II_32 0x00ffffff 559 #define PCI_HT_IDC_IDR_PASSPW 0x40000000 560 #define PCI_HT_IDC_IDR_WEOI 0x80000000 558 #define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */ 559 #define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */ 560 #define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */ 561 561 562 562 /* HyperTransport: Revision ID */ … … 571 571 /* HyperTransport: Extended Configuration Space Access */ 572 572 #define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */ 573 #define PCI_HT_ECSA_ADDR_REG 0x00000ffc 574 #define PCI_HT_ECSA_ADDR_FUN 0x00007000 575 #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 576 #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 577 #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 573 #define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */ 574 #define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */ 575 #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */ 576 #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */ 577 #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */ 578 578 #define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */ 579 579 #define PCI_HT_ECSA_SIZEOF 12 … … 595 595 /* HyperTransport: 40-bit Address Mapping */ 596 596 #define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */ 597 #define PCI_HT_AM40_SBW_BASE 0x000fffff 598 #define PCI_HT_AM40_SBW_CTR 0xf0000000 597 #define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */ 598 #define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */ 599 599 #define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */ 600 600 #define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */ … … 613 613 /* Register indices */ 614 614 #define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */ 615 #define PCI_HT_AM64_W_BASE_LO 0xfff00000 616 #define PCI_HT_AM64_W_CTR 0x0000000f 615 #define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */ 616 #define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */ 617 617 #define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */ 618 618 #define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */ … … 639 639 /* Register indices */ 640 640 #define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */ 641 #define PCI_HT_DR_OTNRD 0x00000001 642 #define PCI_HT_DR_BL_LO 0xffffff00 641 #define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */ 642 #define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */ 643 643 #define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */ 644 644 #define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */ … … 699 699 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ 700 700 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 701 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 702 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 701 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 702 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 703 703 #define PCI_EXP_DEVCTL 0x8 /* Device Control */ 704 704 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ … … 726 726 #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ 727 727 #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ 728 #define PCI_EXP_LNKCAP_PORT 0xff000000 728 #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ 729 729 #define PCI_EXP_LNKCTL 0x10 /* Link Control */ 730 730 #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ … … 748 748 #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ 749 749 #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ 750 #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 751 #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 752 #define PCI_EXP_SLTCAP_PSN 0xfff80000 750 #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */ 751 #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */ 752 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ 753 753 #define PCI_EXP_SLTCTL 0x18 /* Slot Control */ 754 754 #define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */ … … 826 826 #define PCI_PWR_DSR 4 /* Data Select Register */ 827 827 #define PCI_PWR_DATA 8 /* Data Register */ 828 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 829 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 830 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 831 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 832 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 833 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 828 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 829 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 830 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 831 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 832 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 833 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 834 834 #define PCI_PWR_CAP 12 /* Capability */ 835 835 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
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