Changeset 1b20da0 in mainline for kernel/arch/sparc64


Ignore:
Timestamp:
2018-02-28T17:52:03Z (8 years ago)
Author:
Jiří Zárevúcky <zarevucky.jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
3061bc1
Parents:
df6ded8
git-author:
Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:26:03)
git-committer:
Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:52:03)
Message:

style: Remove trailing whitespace on non-empty lines, in certain file types.

Command used: tools/srepl '\([^[:space:]]\)\s\+$' '\1' -- *.c *.h *.py *.sh *.s *.S *.ag

Location:
kernel/arch/sparc64
Files:
59 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/arch/console.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/context_struct.ag

    rdf6ded8 r1b20da0  
    1 # Copyright (c) 2014 Jakub Jermar 
     1# Copyright (c) 2014 Jakub Jermar
    22# All rights reserved.
    33#

  • kernel/arch/sparc64/include/arch/cpu.h

    rdf6ded8 r1b20da0  
    6565
    6666
    67 #endif 
     67#endif
    6868
    6969#endif

  • kernel/arch/sparc64/include/arch/cpu_family.h

    rdf6ded8 r1b20da0  
    4343/**
    4444 * Find the processor (sub)family.
    45  * 
     45 *
    4646 * @return      true iff the CPU belongs to the US family
    4747 */
    … …  
    5555/**
    5656 * Find the processor (sub)family.
    57  * 
     57 *
    5858 * @return      true iff the CPU belongs to the US-III subfamily
    5959 */
    … …  
    6868/**
    6969 * Find the processor (sub)family.
    70  * 
     70 *
    7171 * @return      true iff the CPU belongs to the US-IV subfamily
    7272 */

  • kernel/arch/sparc64/include/arch/cpu_node.h

    rdf6ded8 r1b20da0  
    4343 *  Depending on the machine type (and possibly the OFW version), CPUs can be
    4444 *  at "/" or at "/ssm@0,0".
    45  */ 
     45 */
    4646static inline ofw_tree_node_t *cpus_parent(void)
    4747{

  • kernel/arch/sparc64/include/arch/drivers/fb.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/drivers/niagara.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/drivers/pci.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/fpu_context.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/interrupt.h

    rdf6ded8 r1b20da0  
    4040
    4141#define IVT_ITEMS  512
    42 #define IVT_FIRST  0 
     42#define IVT_FIRST  0
    4343
    4444/* This needs to be defined for inter-architecture API portability. */

  • kernel/arch/sparc64/include/arch/istate_struct.ag

    rdf6ded8 r1b20da0  
    1 # Copyright (c) 2014 Jakub Jermar 
     1# Copyright (c) 2014 Jakub Jermar
    22# All rights reserved.
    33#

  • kernel/arch/sparc64/include/arch/mm/asid.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/mm/mmu.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/mm/page.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/mm/pagesize.h

    rdf6ded8 r1b20da0  
    2828 */
    2929
    30 /** @addtogroup sparc64mm       
     30/** @addtogroup sparc64mm
    3131 * @{
    3232 */

  • kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */
    … …  
    4343/* I-MMU ASIs. */
    4444#define ASI_IMMU                        0x50
    45 #define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
     45#define ASI_IMMU_TSB_8KB_PTR_REG        0x51
    4646#define ASI_IMMU_TSB_64KB_PTR_REG       0x52
    4747#define ASI_ITLB_DATA_IN_REG            0x54
    … …  
    6363/* D-MMU ASIs. */
    6464#define ASI_DMMU                        0x58
    65 #define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
     65#define ASI_DMMU_TSB_8KB_PTR_REG        0x59
    6666#define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
    6767#define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
    … …  
    106106                unsigned vw : 1;
    107107                unsigned : 1;
    108                 unsigned fm : 16;       
     108                unsigned fm : 16;
    109109                unsigned dm : 1;        /**< D-MMU enable. */
    110110                unsigned im : 1;        /**< I-MMU enable. */

  • kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */
    … …  
    143143 * behind this is to prevent careless mistakes in the code
    144144 * caused by setting only the entry number and not the TLB
    145  * number in the US3 code (when taking the code from US). 
     145 * number in the US3 code (when taking the code from US).
    146146 */
    147147
    … …  
    241241
    242242/**
    243  * Determine the number of entries in the DMMU's small TLB. 
     243 * Determine the number of entries in the DMMU's small TLB.
    244244 */
    245245NO_TRACE static inline uint16_t tlb_dsmall_size(void)
    … …  
    249249
    250250/**
    251  * Determine the number of entries in each DMMU's big TLB. 
     251 * Determine the number of entries in each DMMU's big TLB.
    252252 */
    253253NO_TRACE static inline uint16_t tlb_dbig_size(void)
    … …  
    257257
    258258/**
    259  * Determine the number of entries in the IMMU's small TLB. 
     259 * Determine the number of entries in the IMMU's small TLB.
    260260 */
    261261NO_TRACE static inline uint16_t tlb_ismall_size(void)
    … …  
    265265
    266266/**
    267  * Determine the number of entries in the IMMU's big TLB. 
     267 * Determine the number of entries in the IMMU's big TLB.
    268268 */
    269269NO_TRACE static inline uint16_t tlb_ibig_size(void)
    … …  
    449449/** Read DMMU TLB Data Access Register.
    450450 *
    451  * @param tlb           TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) 
     451 * @param tlb           TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
    452452 * @param entry         TLB Entry index.
    453453 *
    … …  
    467467/** Write DMMU TLB Data Access Register.
    468468 *
    469  * @param tlb           TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) 
     469 * @param tlb           TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
    470470 * @param entry         TLB Entry index.
    471471 * @param value         Value to be written.
    … …  
    485485/** Read IMMU TLB Tag Read Register.
    486486 *
    487  * @param tlb           TLB number (one of TLB_ISMALL or TLB_IBIG) 
     487 * @param tlb           TLB number (one of TLB_ISMALL or TLB_IBIG)
    488488 * @param entry         TLB Entry index.
    489489 *
    … …  
    646646        da.vpn = pg.vpn;
    647647       
    648         /* da.value is the address within the ASI */ 
     648        /* da.value is the address within the ASI */
    649649        asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
    650650
    … …  
    672672        da.vpn = pg.vpn;
    673673       
    674         /* da.value is the address within the ASI */ 
     674        /* da.value is the address within the ASI */
    675675        asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
    676676

  • kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/mm/sun4u/tte.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/mm/sun4v/as.h

    rdf6ded8 r1b20da0  
    2828 */
    2929
    30 /** @addtogroup sparc64mm       
     30/** @addtogroup sparc64mm
    3131 * @{
    3232 */
    … …  
    5454 * Even though for sun4v the format of the TSB Tag states that the context
    5555 * field has 16 bits, the T1 CPU still only supports 13-bit contexts and the
    56  * three most significant bits are always zero. 
     56 * three most significant bits are always zero.
    5757 */
    5858typedef union tte_tag {

  • kernel/arch/sparc64/include/arch/mm/sun4v/page.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/mm/tsb.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/mm/tte.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/regdef.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    5858/*
    5959 * The following definitions concern the UPA_CONFIG register on US and the
    60  * FIREPLANE_CONFIG register on US3. 
     60 * FIREPLANE_CONFIG register on US3.
    6161 */
    6262#define ICBUS_CONFIG_MID_SHIFT    17

  • kernel/arch/sparc64/include/arch/register.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    9898        uint64_t value;
    9999        struct {
    100                 uint64_t : 47; 
     100                uint64_t : 47;
    101101                unsigned stick_int : 1;
    102102                unsigned int_level : 15;

  • kernel/arch/sparc64/include/arch/smp/sun4u/ipi.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/smp/sun4v/smp.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/stack.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/sun4u/arch.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/sun4v/arch.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    4747
    4848/* register where the address of the MMU fault status area will be stored */
    49 #define SCRATCHPAD_MMU_FSA      0x00   
     49#define SCRATCHPAD_MMU_FSA      0x00
    5050
    5151/* register where the CPUID will be stored */

  • kernel/arch/sparc64/include/arch/sun4v/ipi.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/sun4v/register.h

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/arch/trap/interrupt.h

    rdf6ded8 r1b20da0  
    3030 * @{
    3131 */
    32 /** 
     32/**
    3333 * @file
    3434 * @brief This file contains level N interrupt and inter-processor interrupt

  • kernel/arch/sparc64/include/arch/trap/regwin.h

    rdf6ded8 r1b20da0  
    8484 */
    8585.macro SPILL_NORMAL_HANDLER_KERNEL
    86         stx %l0, [%sp + STACK_BIAS + L0_OFFSET] 
     86        stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
    8787        stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
    8888        stx %l2, [%sp + STACK_BIAS + L2_OFFSET]

  • kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h

    rdf6ded8 r1b20da0  
    3030 * @{
    3131 */
    32 /** 
     32/**
    3333 * @file
    3434 * @brief This file contains interrupt vector trap handler.

  • kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h

    rdf6ded8 r1b20da0  
    7777        mov VA_IMMU_TAG_ACCESS, %g5
    7878        ldxa [%g5] ASI_IMMU, %g5                        ! read the faulting Context and VPN
    79         PREEMPTIBLE_HANDLER exc_dispatch 
     79        PREEMPTIBLE_HANDLER exc_dispatch
    8080.endm
    8181
    … …  
    143143        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
    144144        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5             ! read the faulting Context and VPN
    145         PREEMPTIBLE_HANDLER exc_dispatch 
     145        PREEMPTIBLE_HANDLER exc_dispatch
    146146.endm
    147147
    … …  
    163163        mov VA_DMMU_TAG_ACCESS, %g5
    164164        ldxa [%g5] ASI_DMMU, %g5                        ! read the faulting Context and VPN
    165         PREEMPTIBLE_HANDLER exc_dispatch 
     165        PREEMPTIBLE_HANDLER exc_dispatch
    166166.endm
    167167

  • kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h

    rdf6ded8 r1b20da0  
    4242 */
    4343.macro SPILL_TO_USPACE_WINDOW_BUFFER
    44         stx %l0, [%g7 + L0_OFFSET]     
     44        stx %l0, [%g7 + L0_OFFSET]
    4545        stx %l1, [%g7 + L1_OFFSET]
    4646        stx %l2, [%g7 + L2_OFFSET]

  • kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h

    rdf6ded8 r1b20da0  
    3030 * @{
    3131 */
    32 /** 
     32/**
    3333 * @file
    3434 * @brief This file contains interrupt vector trap handler.

  • kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h

    rdf6ded8 r1b20da0  
    7575        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
    7676        clr %g5         ! XXX
    77         PREEMPTIBLE_HANDLER exc_dispatch 
     77        PREEMPTIBLE_HANDLER exc_dispatch
    7878.endm
    7979
    … …  
    179179        or %g1, %g3, %g5
    180180
    181         PREEMPTIBLE_HANDLER exc_dispatch 
     181        PREEMPTIBLE_HANDLER exc_dispatch
    182182.endm
    183183#endif /* __ASM__ */

  • kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h

    rdf6ded8 r1b20da0  
    4848        set SCRATCHPAD_WBUF, \tmpreg2
    4949        ldxa [\tmpreg2] ASI_SCRATCHPAD, \tmpreg1
    50         stx %l0, [\tmpreg1 + L0_OFFSET] 
     50        stx %l0, [\tmpreg1 + L0_OFFSET]
    5151        stx %l1, [\tmpreg1 + L1_OFFSET]
    5252        stx %l2, [\tmpreg1 + L2_OFFSET]

  • kernel/arch/sparc64/src/console.c

    rdf6ded8 r1b20da0  
    5656 * Called on UltraSPARC machines with standard keyboard and framebuffer.
    5757 *
    58  * @param aliases       the "/aliases" OBP node 
     58 * @param aliases       the "/aliases" OBP node
    5959 */
    6060static void standard_console_init(ofw_tree_node_t *aliases)
    … …  
    8989/**
    9090 * Initialize input/output. Auto-detects the type of machine
    91  * and calls the appropriate I/O init routine. 
     91 * and calls the appropriate I/O init routine.
    9292 */
    9393void standalone_sparc64_console_init(void)

  • kernel/arch/sparc64/src/context.S

    rdf6ded8 r1b20da0  
    3232#include <arch/regdef.h>
    3333
    34 .text   
     34.text
    3535
    3636/*

  • kernel/arch/sparc64/src/cpu/sun4u/cpu.c

    rdf6ded8 r1b20da0  
    8686         * Detect processor frequency.
    8787         */
    88         if (is_us() || is_us_iii()) { 
     88        if (is_us() || is_us_iii()) {
    8989                node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
    9090                while (node) {
    9191                        int f = find_cpu_frequency(node);
    92                         if (f != -1) 
     92                        if (f != -1)
    9393                                clock_frequency = (uint32_t) f;
    9494                        node = ofw_tree_find_peer_by_device_type(node, "cpu");
    … …  
    100100                        f = find_cpu_frequency(
    101101                                ofw_tree_find_child(node, "cpu@0"));
    102                         if (f != -1) 
     102                        if (f != -1)
    103103                                clock_frequency = (uint32_t) f;
    104104                        f = find_cpu_frequency(
    105105                                ofw_tree_find_child(node, "cpu@1"));
    106                         if (f != -1) 
     106                        if (f != -1)
    107107                                clock_frequency = (uint32_t) f;
    108108                        node = ofw_tree_find_peer_by_name(node, "cmp");

  • kernel/arch/sparc64/src/drivers/pci.c

    rdf6ded8 r1b20da0  
    7979 *
    8080 * @return              Address of the initialized PCI structure.
    81  */ 
     81 */
    8282pci_t *pci_sabre_init(ofw_tree_node_t *node)
    8383{
    … …  
    121121 *
    122122 * @return              Address of the initialized PCI structure.
    123  */ 
     123 */
    124124pci_t *pci_psycho_init(ofw_tree_node_t *node)
    125125{

  • kernel/arch/sparc64/src/drivers/scr.c

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    209209               
    210210                break;
    211         case SCR_FFB:   
     211        case SCR_FFB:
    212212                fb_scanline = 8192;
    213213                visual = VISUAL_BGR_0_8_8_8;

  • kernel/arch/sparc64/src/mm/sun4u/tlb.c

    rdf6ded8 r1b20da0  
    322322                 * Forward the page fault to the address space page fault
    323323                 * handler.
    324                  */             
     324                 */
    325325                as_page_fault(page_16k, PF_ACCESS_WRITE, istate);
    326326        }
    … …  
    330330 *
    331331 * The diag field has been left out in order to make this function more generic
    332  * (there is no diag field in US3 architeture). 
    333  *
    334  * @param i             TLB entry number 
     332 * (there is no diag field in US3 architeture).
     333 *
     334 * @param i             TLB entry number
    335335 * @param t             TLB entry tag
    336  * @param d             TLB entry data 
     336 * @param d             TLB entry data
    337337 */
    338338static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)

  • kernel/arch/sparc64/src/mm/sun4v/tlb.c

    rdf6ded8 r1b20da0  
    282282                 * Forward the page fault to the address space page fault
    283283                 * handler.
    284                  */             
     284                 */
    285285                as_page_fault(va, PF_ACCESS_READ, istate);
    286286        }
    … …  
    323323                 * Forward the page fault to the address space page fault
    324324                 * handler.
    325                  */             
     325                 */
    326326                as_page_fault(va, PF_ACCESS_WRITE, istate);
    327327        }

  • kernel/arch/sparc64/src/mm/sun4v/tsb.c

    rdf6ded8 r1b20da0  
    2828 */
    2929
    30 /** @addtogroup sparc64mm       
     30/** @addtogroup sparc64mm
    3131 * @{
    3232 */
    … …  
    8686
    8787        as = t->as;
    88         index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK; 
     88        index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
    8989       
    9090        tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);

  • kernel/arch/sparc64/src/smp/sun4u/ipi.c

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    122122                        /*
    123123                         * Prevent deadlock.
    124                          */                     
     124                         */
    125125                        (void) interrupts_enable();
    126126                        delay(20 + (tick_read() & 0xff));
    … …  
    180180 * Interrupts must be disabled.
    181181 *
    182  * @param cpu_id Destination cpu id (index into cpus array). Must not 
     182 * @param cpu_id Destination cpu id (index into cpus array). Must not
    183183 *               be the current cpu.
    184184 * @param ipi    IPI number.

  • kernel/arch/sparc64/src/smp/sun4u/smp.c

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    8383 * Wakes up the CPU which is represented by the "node" OFW tree node.
    8484 * If "node" represents the current CPU, calling the function has
    85  * no effect. 
     85 * no effect.
    8686 */
    8787static void wakeup_cpu(ofw_tree_node_t *node)

  • kernel/arch/sparc64/src/smp/sun4u/smp_call.c

    rdf6ded8 r1b20da0  
    4242void arch_smp_call_ipi(unsigned int cpu_id)
    4343{
    44         /* 
     44        /*
    4545         * Required by ipi_unicast_arch(). That functions resolves a potential
    4646         * deadlock should both the destination and source cpus be sending

  • kernel/arch/sparc64/src/smp/sun4v/ipi.c

    rdf6ded8 r1b20da0  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */

  • kernel/arch/sparc64/src/smp/sun4v/smp.c

    rdf6ded8 r1b20da0  
    254254                        exec_unit_assign_error = 1;
    255255                }
    256         }               
     256        }
    257257
    258258        /* save the number of CPUs to a globally accessible variable */

  • kernel/arch/sparc64/src/sun4u/start.S

    rdf6ded8 r1b20da0  
    8888        ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
    8989        sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
    90         srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5     
     90        srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
    9191
    9292        /*
    … …  
    118118        wrpr %g1, %lo(trap_table), %tba
    119119
    120         /* 
     120        /*
    121121         * Take over the DMMU by installing locked TTE entry identically
    122122         * mapping the first 4M of memory.
    … …  
    135135        ! demap context 0
    136136        SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
    137         stxa %g0, [%g1] ASI_DMMU_DEMAP                 
     137        stxa %g0, [%g1] ASI_DMMU_DEMAP
    138138        membar #Sync
    139139
    … …  
    143143        ! write DTLB tag
    144144        SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
    145         stxa %g1, [VA_DMMU_TAG_ACCESS] %asi                     
     145        stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
    146146        membar #Sync
    147147
    … …  
    164164        ! write DTLB data and install the kernel mapping
    165165        SET_TLB_DATA(g1, g2, TTE_L | TTE_W)     ! use non-global mapping
    166         stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG           
     166        stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
    167167        membar #Sync
    168168
    … …  
    175175        ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
    176176        SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
    177         stxa %g1, [VA_DMMU_TAG_ACCESS] %asi                     
     177        stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
    178178        membar #Sync
    179179
    180180        ! write DTLB data and install the kernel mapping in context 1
    181181        SET_TLB_DATA(g1, g2, TTE_W)                     ! use non-global mapping
    182         stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG           
     182        stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
    183183        membar #Sync
    184184       
    … …  
    213213        ! write ITLB data and install the temporary mapping in context 1
    214214        SET_TLB_DATA(g1, g2, 0)                 ! use non-global mapping
    215         stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG           
     215        stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
    216216        flush %g5
    217217       
    … …  
    223223        ! demap context 0
    224224        SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
    225         stxa %g0, [%g1] ASI_IMMU_DEMAP                 
     225        stxa %g0, [%g1] ASI_IMMU_DEMAP
    226226        flush %g5
    227227       
    … …  
    234234        ! write ITLB data and install the permanent kernel mapping in context 0
    235235        SET_TLB_DATA(g1, g2, TTE_L)             ! use non-global mapping
    236         stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG           
     236        stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
    237237        flush %g5
    238238
    … …  
    242242        ! demap context 1
    243243        SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
    244         stxa %g0, [%g1] ASI_IMMU_DEMAP                 
     244        stxa %g0, [%g1] ASI_IMMU_DEMAP
    245245        flush %g5
    246246       
    … …  
    406406 */
    407407
    408 .align 32 
     408.align 32
    409409/*
    410410 * This label is used by the fast_data_access_MMU_miss trap handler.
    … …  
    417417 */
    418418SYMBOL(end_of_identity)
    419         .quad -1 
     419        .quad -1
    420420/*
    421421 * This variable is used by the fast_data_access_MMU_miss trap handler.

  • kernel/arch/sparc64/src/sun4v/md.c

    rdf6ded8 r1b20da0  
    126126 * Returns the value of the integer property of the given node.
    127127 *
    128  * @param 
     128 * @param
    129129 */
    130130bool md_get_integer_property(md_node_t node, const char *key,
    131131        uint64_t *result)
    132132{
    133         element_idx_t idx = node;       
     133        element_idx_t idx = node;
    134134
    135135        while (get_element(idx)->tag != NODE_END) {
    … …  
    149149 * Returns the value of the string property of the given node.
    150150 *
    151  * @param 
     151 * @param
    152152 */
    153153bool md_get_string_property(md_node_t node, const char *key,
    … …  
    278278/**
    279279 * Moves "node" to the node following "node" in the list of all the existing
    280  * nodes of the MD whose name is "name". 
     280 * nodes of the MD whose name is "name".
    281281 */
    282282bool md_next_node(md_node_t *node, const char *name)

  • kernel/arch/sparc64/src/sun4v/start.S

    rdf6ded8 r1b20da0  
    118118        ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
    119119        sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
    120         srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5     
     120        srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
    121121
    122122        /*
    … …  
    225225         * Save physmem_base for use by the mm subsystem.
    226226         * %l6 contains starting physical address
    227          */     
     227         */
    228228        sethi %hi(physmem_base), %l4
    229229        stx %l6, [%l4 + %lo(physmem_base)]

  • kernel/arch/sparc64/src/trap/interrupt.c

    rdf6ded8 r1b20da0  
    112112        exc_register(TT_TAG_OVERFLOW,
    113113            "tag_overflow", false,
    114             tag_overflow);     
     114            tag_overflow);
    115115        exc_register(TT_DIVISION_BY_ZERO,
    116116            "division_by_zero", false,
    … …  
    145145            tick_interrupt);
    146146
    147 #ifdef SUN4U 
     147#ifdef SUN4U
    148148        exc_register(TT_INTERRUPT_VECTOR_TRAP,
    149149            "interrupt_vector_trap", true,
    … …  
    159159        exc_register(TT_FAST_DATA_ACCESS_PROTECTION,
    160160            "fast_data_access_protection", true,
    161             fast_data_access_protection);       
     161            fast_data_access_protection);
    162162
    163163#ifdef SUN4V

  • kernel/arch/sparc64/src/trap/sun4u/trap_table.S

    rdf6ded8 r1b20da0  
    6464        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
    6565        clr %g5
    66         PREEMPTIBLE_HANDLER exc_dispatch 
     66        PREEMPTIBLE_HANDLER exc_dispatch
    6767
    6868/* TT = 0x0a, TL = 0, instruction_access_error */
    … …  
    7171        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
    7272        clr %g5
    73         PREEMPTIBLE_HANDLER exc_dispatch 
     73        PREEMPTIBLE_HANDLER exc_dispatch
    7474
    7575/* TT = 0x10, TL = 0, illegal_instruction */
    … …  
    7878        mov TT_ILLEGAL_INSTRUCTION, %g2
    7979        clr %g5
    80         PREEMPTIBLE_HANDLER exc_dispatch 
     80        PREEMPTIBLE_HANDLER exc_dispatch
    8181
    8282/* TT = 0x11, TL = 0, privileged_opcode */
    … …  
    8585        mov TT_PRIVILEGED_OPCODE, %g2
    8686        clr %g5
    87         PREEMPTIBLE_HANDLER exc_dispatch 
     87        PREEMPTIBLE_HANDLER exc_dispatch
    8888
    8989/* TT = 0x12, TL = 0, unimplemented_LDD */
    … …  
    9292        mov TT_UNIMPLEMENTED_LDD, %g2
    9393        clr %g5
    94         PREEMPTIBLE_HANDLER exc_dispatch 
     94        PREEMPTIBLE_HANDLER exc_dispatch
    9595
    9696/* TT = 0x13, TL = 0, unimplemented_STD */
    … …  
    106106        mov TT_FP_DISABLED, %g2
    107107        clr %g5
    108         PREEMPTIBLE_HANDLER exc_dispatch 
     108        PREEMPTIBLE_HANDLER exc_dispatch
    109109
    110110/* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
    … …  
    168168        mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
    169169        clr %g5
    170         PREEMPTIBLE_HANDLER exc_dispatch 
     170        PREEMPTIBLE_HANDLER exc_dispatch
    171171
    172172/* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
    … …  
    382382        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
    383383        clr %g5
    384         PREEMPTIBLE_HANDLER exc_dispatch 
     384        PREEMPTIBLE_HANDLER exc_dispatch
    385385
    386386/* TT = 0x0a, TL > 0, instruction_access_error */
    … …  
    489489 * TL1: preemptible trap handler started after a tick interrupt
    490490 * TL2: preemptible trap handler did SAVE
    491  * TL3: spill handler touched the kernel stack 
     491 * TL3: spill handler touched the kernel stack
    492492 * TL4: hardware or software failure
    493493 *
    … …  
    510510         * trap is resolved. However, because we are in the wrong window from the
    511511         * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
    512          */ 
     512         */
    513513        and %g3, TSTATE_CWP_MASK, %g4
    514514        wrpr %g4, 0, %cwp                       ! resynchronize CWP
    … …  
    566566
    567567        /*
    568          * At this moment, we are using the kernel stack 
     568         * At this moment, we are using the kernel stack
    569569         * and have successfully allocated a register window.
    570570         */
    … …  
    585585.else
    586586        ! store the syscall number on the stack as 7th argument
    587         stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6] 
     587        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
    588588.endif
    589589

  • kernel/arch/sparc64/src/trap/sun4v/trap_table.S

    rdf6ded8 r1b20da0  
    6767        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
    6868        clr %g5
    69         PREEMPTIBLE_HANDLER exc_dispatch 
     69        PREEMPTIBLE_HANDLER exc_dispatch
    7070
    7171/* TT = 0x09, TL = 0, instruction_access_mmu_miss */
    … …  
    8686        mov TT_IAE_UNAUTH_ACCESS, %g2
    8787        clr %g5
    88         PREEMPTIBLE_HANDLER exc_dispatch 
     88        PREEMPTIBLE_HANDLER exc_dispatch
    8989
    9090/* TT = 0x0c, TL = 0, IAE_nfo_page */
    … …  
    9393        mov TT_IAE_NFO_PAGE, %g2
    9494        clr %g5
    95         PREEMPTIBLE_HANDLER exc_dispatch 
     95        PREEMPTIBLE_HANDLER exc_dispatch
    9696
    9797/* TT = 0x10, TL = 0, illegal_instruction */
    … …  
    100100        mov TT_ILLEGAL_INSTRUCTION, %g2
    101101        clr %g5
    102         PREEMPTIBLE_HANDLER exc_dispatch 
     102        PREEMPTIBLE_HANDLER exc_dispatch
    103103
    104104/* TT = 0x11, TL = 0, privileged_opcode */
    … …  
    107107        mov TT_PRIVILEGED_OPCODE, %g2
    108108        clr %g5
    109         PREEMPTIBLE_HANDLER exc_dispatch 
     109        PREEMPTIBLE_HANDLER exc_dispatch
    110110
    111111/* TT = 0x12, TL = 0, unimplemented_LDD */
    … …  
    114114        mov TT_UNIMPLEMENTED_LDD, %g2
    115115        clr %g5
    116         PREEMPTIBLE_HANDLER exc_dispatch 
     116        PREEMPTIBLE_HANDLER exc_dispatch
    117117
    118118/* TT = 0x13, TL = 0, unimplemented_STD */
    … …  
    121121        mov TT_UNIMPLEMENTED_STD, %g2
    122122        clr %g5
    123         PREEMPTIBLE_HANDLER exc_dispatch 
     123        PREEMPTIBLE_HANDLER exc_dispatch
    124124
    125125/* TT = 0x14, TL = 0, DAE_invalid_asi */
    … …  
    128128        mov TT_DAE_INVALID_ASI, %g2
    129129        clr %g5
    130         PREEMPTIBLE_HANDLER exc_dispatch 
     130        PREEMPTIBLE_HANDLER exc_dispatch
    131131
    132132/* TT = 0x15, TL = 0, DAE_privilege_violation */
    … …  
    135135        mov TT_DAE_PRIVILEGE_VIOLATION, %g2
    136136        clr %g5
    137         PREEMPTIBLE_HANDLER exc_dispatch 
     137        PREEMPTIBLE_HANDLER exc_dispatch
    138138
    139139/* TT = 0x16, TL = 0, DAE_nc_page */
    … …  
    142142        mov TT_DAE_NC_PAGE, %g2
    143143        clr %g5
    144         PREEMPTIBLE_HANDLER exc_dispatch 
     144        PREEMPTIBLE_HANDLER exc_dispatch
    145145
    146146/* TT = 0x17, TL = 0, DAE_nfo_page */
    … …  
    149149        mov TT_DAE_NFO_PAGE, %g2
    150150        clr %g5
    151         PREEMPTIBLE_HANDLER exc_dispatch 
     151        PREEMPTIBLE_HANDLER exc_dispatch
    152152
    153153/* TT = 0x20, TL = 0, fb_disabled handler */
    … …  
    156156        mov TT_FP_DISABLED, %g2
    157157        clr %g5
    158         PREEMPTIBLE_HANDLER exc_dispatch 
     158        PREEMPTIBLE_HANDLER exc_dispatch
    159159
    160160/* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
    … …  
    163163        mov TT_FP_EXCEPTION_IEEE_754, %g2
    164164        clr %g5
    165         PREEMPTIBLE_HANDLER exc_dispatch 
     165        PREEMPTIBLE_HANDLER exc_dispatch
    166166
    167167/* TT = 0x22, TL = 0, fb_exception_other handler */
    … …  
    170170        mov TT_FP_EXCEPTION_OTHER, %g2
    171171        clr %g5
    172         PREEMPTIBLE_HANDLER exc_dispatch 
     172        PREEMPTIBLE_HANDLER exc_dispatch
    173173
    174174/* TT = 0x23, TL = 0, tag_overflow */
    … …  
    177177        mov TT_TAG_OVERFLOW, %g2
    178178        clr %g5
    179         PREEMPTIBLE_HANDLER exc_dispatch 
     179        PREEMPTIBLE_HANDLER exc_dispatch
    180180
    181181/* TT = 0x24, TL = 0, clean_window handler */
    … …  
    189189        mov TT_DIVISION_BY_ZERO, %g2
    190190        clr %g5
    191         PREEMPTIBLE_HANDLER exc_dispatch 
     191        PREEMPTIBLE_HANDLER exc_dispatch
    192192
    193193/* TT = 0x30, TL = 0, data_access_exception */
    … …  
    197197        mov TT_DATA_ACCESS_EXCEPTION, %g2
    198198        clr %g5
    199         PREEMPTIBLE_HANDLER exc_dispatch 
     199        PREEMPTIBLE_HANDLER exc_dispatch
    200200
    201201/* TT = 0x31, TL = 0, data_access_mmu_miss */
    … …  
    209209        mov TT_DATA_ACCESS_ERROR, %g2
    210210        clr %g5
    211         PREEMPTIBLE_HANDLER exc_dispatch 
     211        PREEMPTIBLE_HANDLER exc_dispatch
    212212
    213213/* TT = 0x34, TL = 0, mem_address_not_aligned */
    … …  
    216216        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
    217217        clr %g5
    218         PREEMPTIBLE_HANDLER exc_dispatch 
     218        PREEMPTIBLE_HANDLER exc_dispatch
    219219
    220220/* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
    … …  
    223223        mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
    224224        clr %g5
    225         PREEMPTIBLE_HANDLER exc_dispatch 
     225        PREEMPTIBLE_HANDLER exc_dispatch
    226226
    227227/* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
    … …  
    230230        mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
    231231        clr %g5
    232         PREEMPTIBLE_HANDLER exc_dispatch 
     232        PREEMPTIBLE_HANDLER exc_dispatch
    233233
    234234/* TT = 0x37, TL = 0, privileged_action */
    … …  
    237237        mov TT_PRIVILEGED_ACTION, %g2
    238238        clr %g5
    239         PREEMPTIBLE_HANDLER exc_dispatch 
     239        PREEMPTIBLE_HANDLER exc_dispatch
    240240
    241241/* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
    … …  
    244244        mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
    245245        clr %g5
    246         PREEMPTIBLE_HANDLER exc_dispatch 
     246        PREEMPTIBLE_HANDLER exc_dispatch
    247247
    248248/* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
    … …  
    251251        mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
    252252        clr %g5
    253         PREEMPTIBLE_HANDLER exc_dispatch 
     253        PREEMPTIBLE_HANDLER exc_dispatch
    254254
    255255/* TT = 0x41, TL = 0, interrupt_level_1 handler */
    … …  
    378378        mov TT_CPU_MONDO, %g2
    379379        clr %g5
    380         PREEMPTIBLE_HANDLER exc_dispatch 
     380        PREEMPTIBLE_HANDLER exc_dispatch
    381381
    382382/* TT = 0x80, TL = 0, spill_0_normal handler */
    … …  
    437437        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
    438438        clr %g5
    439         PREEMPTIBLE_HANDLER exc_dispatch 
     439        PREEMPTIBLE_HANDLER exc_dispatch
    440440
    441441/* TT = 0x09, TL > 0, instruction_access_mmu_miss */
    … …  
    451451        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
    452452        clr %g5
    453         PREEMPTIBLE_HANDLER exc_dispatch 
     453        PREEMPTIBLE_HANDLER exc_dispatch
    454454
    455455/* TT = 0x0b, TL > 0, IAE_unauth_access */
    … …  
    459459        mov TT_IAE_UNAUTH_ACCESS, %g2
    460460        clr %g5
    461         PREEMPTIBLE_HANDLER exc_dispatch 
     461        PREEMPTIBLE_HANDLER exc_dispatch
    462462
    463463/* TT = 0x0c, TL > 0, IAE_nfo_page */
    … …  
    467467        mov TT_IAE_NFO_PAGE, %g2
    468468        clr %g5
    469         PREEMPTIBLE_HANDLER exc_dispatch 
     469        PREEMPTIBLE_HANDLER exc_dispatch
    470470
    471471/* TT = 0x10, TL > 0, illegal_instruction */
    … …  
    475475        mov TT_ILLEGAL_INSTRUCTION, %g2
    476476        clr %g5
    477         PREEMPTIBLE_HANDLER exc_dispatch 
     477        PREEMPTIBLE_HANDLER exc_dispatch
    478478
    479479/* TT = 0x14, TL > 0, DAE_invalid_asi */
    … …  
    483483        mov TT_DAE_INVALID_ASI, %g2
    484484        clr %g5
    485         PREEMPTIBLE_HANDLER exc_dispatch 
     485        PREEMPTIBLE_HANDLER exc_dispatch
    486486
    487487/* TT = 0x15, TL > 0, DAE_privilege_violation */
    … …  
    491491        mov TT_DAE_PRIVILEGE_VIOLATION, %g2
    492492        clr %g5
    493         PREEMPTIBLE_HANDLER exc_dispatch 
     493        PREEMPTIBLE_HANDLER exc_dispatch
    494494
    495495/* TT = 0x16, TL > 0, DAE_nc_page */
    … …  
    499499        mov TT_DAE_NC_PAGE, %g2
    500500        clr %g5
    501         PREEMPTIBLE_HANDLER exc_dispatch 
     501        PREEMPTIBLE_HANDLER exc_dispatch
    502502
    503503/* TT = 0x17, TL > 0, DAE_nfo_page */
    … …  
    507507        mov TT_DAE_NFO_PAGE, %g2
    508508        clr %g5
    509         PREEMPTIBLE_HANDLER exc_dispatch 
     509        PREEMPTIBLE_HANDLER exc_dispatch
    510510
    511511/* TT = 0x24, TL > 0, clean_window handler */
    … …  
    520520        mov TT_DIVISION_BY_ZERO, %g2
    521521        clr %g5
    522         PREEMPTIBLE_HANDLER exc_dispatch 
     522        PREEMPTIBLE_HANDLER exc_dispatch
    523523
    524524/* TT = 0x30, TL > 0, data_access_exception */
    … …  
    528528        mov TT_DATA_ACCESS_EXCEPTION, %g2
    529529        clr %g5
    530         PREEMPTIBLE_HANDLER exc_dispatch 
     530        PREEMPTIBLE_HANDLER exc_dispatch
    531531
    532532/* TT = 0x31, TL > 0, data_access_mmu_miss */
    … …  
    541541        mov TT_DATA_ACCESS_ERROR, %g2
    542542        clr %g5
    543         PREEMPTIBLE_HANDLER exc_dispatch 
     543        PREEMPTIBLE_HANDLER exc_dispatch
    544544
    545545/* TT = 0x34, TL > 0, mem_address_not_aligned */
    … …  
    549549        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
    550550        clr %g5
    551         PREEMPTIBLE_HANDLER exc_dispatch 
     551        PREEMPTIBLE_HANDLER exc_dispatch
    552552
    553553/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
    … …  
    567567        mov TT_CPU_MONDO, %g2
    568568        clr %g5
    569         PREEMPTIBLE_HANDLER exc_dispatch 
     569        PREEMPTIBLE_HANDLER exc_dispatch
    570570
    571571/* TT = 0x80, TL > 0, spill_0_normal handler */
    … …  
    595595 * Spills the window at CWP + 2 to the kernel stack. This macro is to be
    596596 * used before doing SAVE when the spill trap is undesirable.
    597  * 
     597 *
    598598 * Parameters:
    599599 *      tmpreg1         global register to be used for scratching purposes
    … …  
    608608       
    609609        ! spill to kernel stack
    610         stx %l0, [%sp + STACK_BIAS + L0_OFFSET] 
     610        stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
    611611        stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
    612612        stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
    … …  
    634634 * Fill the window at CWP - 1 from the kernel stack. This macro is to be
    635635 * used before doing RESTORE when the fill trap is undesirable.
    636  * 
     636 *
    637637 * Parameters:
    638638 *      tmpreg1         global register to be used for scratching purposes
    … …  
    689689.else
    690690        ! store the syscall number on the stack as 7th argument
    691         stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6] 
     691        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
    692692.endif
    693693
    … …  
    859859 * Spills the window at CWP + 2 to the userspace window buffer. This macro
    860860 * is to be used before doing SAVE when the spill trap is undesirable.
    861  * 
     861 *
    862862 * Parameters:
    863863 *      tmpreg1         global register to be used for scratching purposes
    … …  
    892892         * trap is resolved. However, because we are in the wrong window from the
    893893         * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
    894          */ 
     894         */
    895895.if NOT(\is_syscall)
    896896        rdpr %tstate, %g3
    … …  
    927927.endif
    928928
    929         mov VA_PRIMARY_CONTEXT_REG, %l0 
     929        mov VA_PRIMARY_CONTEXT_REG, %l0
    930930        stxa %g0, [%l0] ASI_PRIMARY_CONTEXT_REG
    931931        rd %pc, %l0
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