Changeset 1b20da0 in mainline for kernel/arch/ia32/src

Timestamp:

2018-02-28T17:52:03Z (7 years ago)

Author:

Jiří Zárevúcky <zarevucky.jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

3061bc1

Parents:

df6ded8

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:26:03)

git-committer:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:52:03)

Message:

style: Remove trailing whitespace on non-empty lines, in certain file types.

Command used: tools/srepl '\([^[:space:]]\)\s\+$' '\1' -- *.c *.h *.py *.sh *.s *.S *.ag

Location:

kernel/arch/ia32/src

Files:

• asm.S (modified) (3 diffs)
• atomic.S (modified) (2 diffs)
• context.S (modified) (1 diff)
• cpu/cpu.c (modified) (2 diffs)
• smp/ap.S (modified) (1 diff)
• smp/smp.c (modified) (1 diff)
• vreg.c (modified) (1 diff)

kernel/arch/ia32/src/asm.S

@@ -139 +139 @@
  * and without the error word.
  */
-#define ISTATE_SOFT_SIZE        ISTATE_SIZE - (6 * 4) 
+#define ISTATE_SOFT_SIZE        ISTATE_SIZE - (6 * 4)
 
 /*
@@ -329 +329 @@
         .else
                 /*
-                 * Interrupt: fake up an error word 
+                 * Interrupt: fake up an error word
                  */
                 subl $(ISTATE_SOFT_SIZE + 4), %esp
@@ -433 +433 @@
 
 interrupt_handlers:
-.irp cnt, LIST_0_63 
+.irp cnt, LIST_0_63
         handler \cnt
 .endr

kernel/arch/ia32/src/atomic.S

@@ -34 +34 @@
 
 #
-# This is a bus-and-hyperthreading-friendly implementation of spinlock 
+# This is a bus-and-hyperthreading-friendly implementation of spinlock
 #
 FUNCTION_BEGIN(spinlock_arch)
@@ -42 +42 @@
         movl 12(%esp),%ebx
 
-0:      
+0:
         pause                   # Pentium 4's with HT love this instruction
         movl (%ebx),%eax

kernel/arch/ia32/src/context.S

@@ -39 +39 @@
 #
 FUNCTION_BEGIN(context_save_arch)
-        movl 0(%esp), %eax      # save pc value into eax        
-        movl 4(%esp), %edx      # address of the context variable to save context to 
+        movl 0(%esp), %eax      # save pc value into eax
+        movl 4(%esp), %edx      # address of the context variable to save context to
 
         # save registers to given structure

kernel/arch/ia32/src/cpu/cpu.c

@@ -72 +72 @@
 void fpu_disable(void)
 {
-        write_cr0(read_cr0() & ~CR0_TS); 
+        write_cr0(read_cr0() & ~CR0_TS);
 }
 
 void fpu_enable(void)
 {
-        write_cr0(read_cr0() | CR0_TS); 
+        write_cr0(read_cr0() | CR0_TS);
 }
 
@@ -150 +150 @@
 void cpu_print_report(cpu_t* cpu)
 {
-        printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16 
+        printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16
                 " MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
                 cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);

kernel/arch/ia32/src/smp/ap.S

@@ -47 +47 @@
 KDATA=16
 
-/* 
+/*
  * This piece of code is real-mode and is meant to be aligned at 4K boundary.
  * The requirement for such an alignment comes from MP Specification's

kernel/arch/ia32/src/smp/smp.c

@@ -106 +106 @@
 
         /*
-         * SMP initialized, cpus array allocated. Assign each CPU its 
+         * SMP initialized, cpus array allocated. Assign each CPU its
          * physical APIC ID.
          */

kernel/arch/ia32/src/vreg.c

@@ -75 +75 @@
         gs_load(GDT_SELECTOR(VREG_DES));
 
-        vreg_ptr = NULL; 
+        vreg_ptr = NULL;
 }