Changeset 18b6a88 in mainline for uspace/lib/c/arch

Timestamp:

2018-04-15T09:35:04Z (7 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

c1f44ca

Parents:

8ebe212

Message:

More ccheck fixes, sometimes with manual intervention.

Location:

uspace/lib/c/arch

Files:

• mips32/include/libarch/tls.h (modified) (1 diff)
• sparc64/include/libarch/syscall.h (modified) (1 diff)

uspace/lib/c/arch/mips32/include/libarch/tls.h

@@ -69 +69 @@
         tp += MIPS_TP_OFFSET + sizeof(tcb_t);
 
-        asm volatile ("add $27, %0, $0" : : "r"(tp)); /* Move tls to K1 */
+        asm volatile ("add $27, %0, $0" : : "r" (tp)); /* Move tls to K1 */
 }
 
-static inline tcb_t * __tcb_get(void)
+static inline tcb_t *__tcb_get(void)
 {
-        void * retval;
+        void *retval;
 
-        asm volatile("add %0, $27, $0" : "=r"(retval));
+        asm volatile ("add %0, $27, $0" : "=r" (retval));
 
         return (tcb_t *)(retval - MIPS_TP_OFFSET - sizeof(tcb_t));

uspace/lib/c/arch/sparc64/include/libarch/syscall.h

@@ -60 +60 @@
 
         asm volatile (
-                "ta %7\n"
-                : "=r" (a1)
-                : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
-                  "i" (id)
-                : "memory"
+            "ta %7\n"
+            : "=r" (a1)
+            : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
+              "i" (id)
+            : "memory"
         );