Changeset 1433ecda in mainline for kernel/arch/mips32

Timestamp:

2018-04-04T15:42:37Z (8 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2c4e1cc

Parents:

47b2d7e3

Message:

Fix cstyle: make ccheck-fix and commit only files where all the changes are good.

Location:

kernel/arch/mips32

Files:

• include/arch/atomic.h (modified) (3 diffs)
• src/cpu/cpu.c (modified) (2 diffs)
• src/mach/malta/malta.c (modified) (1 diff)
• src/mips32.c (modified) (3 diffs)
• src/mm/frame.c (modified) (1 diff)

kernel/arch/mips32/include/arch/atomic.h

@@ -62 +62 @@
 
         asm volatile (
-                "1:\n"
-                "       ll %0, %1\n"
-                "       addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
-                "       move %2, %0\n"
-                "       sc %0, %1\n"
-                "       beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
-                "       nop\n"
-                : "=&r" (tmp),
-                  "+m" (val->count),
-                  "=&r" (v)
-                : "r" (i),
-                  "i" (0)
+            "1:\n"
+            "   ll %0, %1\n"
+            "   addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
+            "   move %2, %0\n"
+            "   sc %0, %1\n"
+            "   beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
+            "   nop\n"
+            : "=&r" (tmp),
+              "+m" (val->count),
+              "=&r" (v)
+            : "r" (i),
+              "i" (0)
         );
 
@@ -85 +85 @@
 
         asm volatile (
-                "1:\n"
-                "       ll %2, %1\n"
-                "       bnez %2, 2f\n"
-                "       li %0, %3\n"
-                "       sc %0, %1\n"
-                "       beqz %0, 1b\n"
-                "       nop\n"
-                "2:\n"
-                : "=&r" (tmp),
-                  "+m" (val->count),
-                  "=&r" (v)
-                : "i" (1)
+            "1:\n"
+            "   ll %2, %1\n"
+            "   bnez %2, 2f\n"
+            "   li %0, %3\n"
+            "   sc %0, %1\n"
+            "   beqz %0, 1b\n"
+            "   nop\n"
+            "2:\n"
+            : "=&r" (tmp),
+              "+m" (val->count),
+              "=&r" (v)
+            : "i" (1)
         );
 
@@ -105 +105 @@
 {
         do {
-                while (val->count);
+                while (val->count)
+                        ;
         } while (test_and_set(val));
 }

kernel/arch/mips32/src/cpu/cpu.c

@@ -86 +86 @@
 static struct data_t imp_data80[] = {
         { "MIPS", "4Kc" },  /* 0x80 */
-        {"Invalid","Invalid"}, /* 0x81 */
-        {"Invalid","Invalid"}, /* 0x82 */
-        {"MIPS","4Km & 4Kp"}, /* 0x83 */
-        { NULL, NULL}
+        { "Invalid", "Invalid" }, /* 0x81 */
+        { "Invalid", "Invalid" }, /* 0x82 */
+        { "MIPS", "4Km & 4Kp" }, /* 0x83 */
+        { NULL, NULL }
 };
 
@@ -129 +129 @@
 
         printf("cpu%u: %s %s (rev=%d.%d, imp=%d)\n",
-                m->id, data->vendor, data->model, m->arch.rev_num >> 4,
-                m->arch.rev_num & 0x0f, m->arch.imp_num);
+            m->id, data->vendor, data->model, m->arch.rev_num >> 4,
+            m->arch.rev_num & 0x0f, m->arch.imp_num);
 }
 

kernel/arch/mips32/src/mach/malta/malta.c

@@ -84 +84 @@
 {
 
-        const char ch = (char) wch;
+        const char ch = (char) wch;
 
-        (*yamon_print_count)(0, &ch, 1);
+        (*yamon_print_count)(0, &ch, 1);
 }
 

kernel/arch/mips32/src/mips32.c

@@ -74 +74 @@
 
 /* Stack pointer saved when entering user mode */
-uintptr_t supervisor_sp __attribute__ ((section (".text")));
+uintptr_t supervisor_sp __attribute__((section(".text")));
 
 size_t cpu_count = 0;
@@ -172 +172 @@
             (uintptr_t) kernel_uarg->uspace_entry);
 
-        while (1);
+        while (1)
+                ;
 }
 
@@ -194 +195 @@
 {
         ___halt();
-        while (1);
+        while (1)
+                ;
 }
 

kernel/arch/mips32/src/mm/frame.c

@@ -290 +290 @@
         for (i = 0; i < phys_regions_count; i++) {
                 printf("%#010x %10u\n",
-                        PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));
+                    PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));
         }
 }