Changeset 1433ecda in mainline for kernel/arch/ia64/include
- Timestamp:
- 2018-04-04T15:42:37Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 2c4e1cc
- Parents:
- 47b2d7e3
- Location:
- kernel/arch/ia64/include/arch
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia64/include/arch/asm.h
r47b2d7e3 r1433ecda 60 60 61 61 asm volatile ( 62 "mf\n"63 "mf.a\n"64 ::: "memory"62 "mf\n" 63 "mf.a\n" 64 ::: "memory" 65 65 ); 66 66 } … … 74 74 75 75 asm volatile ( 76 "mf\n"77 "mf.a\n"78 ::: "memory"76 "mf\n" 77 "mf.a\n" 78 ::: "memory" 79 79 ); 80 80 } … … 88 88 89 89 asm volatile ( 90 "mf\n"91 "mf.a\n"92 ::: "memory"90 "mf\n" 91 "mf.a\n" 92 ::: "memory" 93 93 ); 94 94 } … … 99 99 100 100 asm volatile ( 101 "mf\n"102 ::: "memory"101 "mf\n" 102 ::: "memory" 103 103 ); 104 104 … … 109 109 110 110 asm volatile ( 111 "mf.a\n"112 ::: "memory"111 "mf.a\n" 112 ::: "memory" 113 113 ); 114 114 … … 121 121 122 122 asm volatile ( 123 "mf\n"124 ::: "memory"123 "mf\n" 124 ::: "memory" 125 125 ); 126 126 … … 131 131 132 132 asm volatile ( 133 "mf.a\n"134 ::: "memory"133 "mf.a\n" 134 ::: "memory" 135 135 ); 136 136 … … 143 143 144 144 asm volatile ( 145 "mf\n"146 ::: "memory"145 "mf\n" 146 ::: "memory" 147 147 ); 148 148 … … 153 153 154 154 asm volatile ( 155 "mf.a\n"156 ::: "memory"155 "mf.a\n" 156 ::: "memory" 157 157 ); 158 158 … … 171 171 172 172 asm volatile ( 173 "mov %[value] = r12"174 : [value] "=r" (value)173 "mov %[value] = r12" 174 : [value] "=r" (value) 175 175 ); 176 176 … … 188 188 189 189 asm volatile ( 190 "mov %[value] = psr\n"191 : [value] "=r" (v)190 "mov %[value] = psr\n" 191 : [value] "=r" (v) 192 192 ); 193 193 … … 205 205 206 206 asm volatile ( 207 "mov %[value] = cr.iva\n"208 : [value] "=r" (v)207 "mov %[value] = cr.iva\n" 208 : [value] "=r" (v) 209 209 ); 210 210 … … 220 220 { 221 221 asm volatile ( 222 "mov cr.iva = %[value]\n"223 :: [value] "r" (v)222 "mov cr.iva = %[value]\n" 223 :: [value] "r" (v) 224 224 ); 225 225 } … … 236 236 237 237 asm volatile ( 238 "mov %[value] = cr.ivr\n"239 : [value] "=r" (v)238 "mov %[value] = cr.ivr\n" 239 : [value] "=r" (v) 240 240 ); 241 241 … … 248 248 249 249 asm volatile ( 250 "mov %[value] = cr64\n"251 : [value] "=r" (v)250 "mov %[value] = cr64\n" 251 : [value] "=r" (v) 252 252 ); 253 253 … … 263 263 { 264 264 asm volatile ( 265 "mov ar.itc = %[value]\n"266 :: [value] "r" (v)265 "mov ar.itc = %[value]\n" 266 :: [value] "r" (v) 267 267 ); 268 268 } … … 278 278 279 279 asm volatile ( 280 "mov %[value] = ar.itc\n"281 : [value] "=r" (v)280 "mov %[value] = ar.itc\n" 281 : [value] "=r" (v) 282 282 ); 283 283 … … 293 293 { 294 294 asm volatile ( 295 "mov cr.itm = %[value]\n"296 :: [value] "r" (v)295 "mov cr.itm = %[value]\n" 296 :: [value] "r" (v) 297 297 ); 298 298 } … … 308 308 309 309 asm volatile ( 310 "mov %[value] = cr.itm\n"311 : [value] "=r" (v)310 "mov %[value] = cr.itm\n" 311 : [value] "=r" (v) 312 312 ); 313 313 … … 325 325 326 326 asm volatile ( 327 "mov %[value] = cr.itv\n"328 : [value] "=r" (v)327 "mov %[value] = cr.itv\n" 328 : [value] "=r" (v) 329 329 ); 330 330 … … 340 340 { 341 341 asm volatile ( 342 "mov cr.itv = %[value]\n"343 :: [value] "r" (v)342 "mov cr.itv = %[value]\n" 343 :: [value] "r" (v) 344 344 ); 345 345 } … … 353 353 { 354 354 asm volatile ( 355 "mov cr.eoi = %[value]\n"356 :: [value] "r" (v)355 "mov cr.eoi = %[value]\n" 356 :: [value] "r" (v) 357 357 ); 358 358 } … … 368 368 369 369 asm volatile ( 370 "mov %[value] = cr.tpr\n"371 : [value] "=r" (v)370 "mov %[value] = cr.tpr\n" 371 : [value] "=r" (v) 372 372 ); 373 373 … … 383 383 { 384 384 asm volatile ( 385 "mov cr.tpr = %[value]\n"386 :: [value] "r" (v)385 "mov cr.tpr = %[value]\n" 386 :: [value] "r" (v) 387 387 ); 388 388 } … … 401 401 402 402 asm volatile ( 403 "mov %[value] = psr\n"404 "rsm %[mask]\n"405 : [value] "=r" (v)406 : [mask] "i" (PSR_I_MASK)403 "mov %[value] = psr\n" 404 "rsm %[mask]\n" 405 : [value] "=r" (v) 406 : [mask] "i" (PSR_I_MASK) 407 407 ); 408 408 … … 423 423 424 424 asm volatile ( 425 "mov %[value] = psr\n"426 "ssm %[mask]\n"427 ";;\n"428 "srlz.d\n"429 : [value] "=r" (v)430 : [mask] "i" (PSR_I_MASK)425 "mov %[value] = psr\n" 426 "ssm %[mask]\n" 427 ";;\n" 428 "srlz.d\n" 429 : [value] "=r" (v) 430 : [mask] "i" (PSR_I_MASK) 431 431 ); 432 432 … … 473 473 { 474 474 asm volatile ( 475 "rsm %[mask]\n"476 ";;\n"477 "srlz.d\n"478 :: [mask] "i" (PSR_PK_MASK)475 "rsm %[mask]\n" 476 ";;\n" 477 "srlz.d\n" 478 :: [mask] "i" (PSR_PK_MASK) 479 479 ); 480 480 } -
kernel/arch/ia64/include/arch/atomic.h
r47b2d7e3 r1433ecda 43 43 44 44 asm volatile ( 45 "movl %[v] = 0x1;;\n"46 "xchg8 %[v] = %[count], %[v];;\n"47 : [v] "=r" (v),48 [count] "+m" (val->count)45 "movl %[v] = 0x1;;\n" 46 "xchg8 %[v] = %[count], %[v];;\n" 47 : [v] "=r" (v), 48 [count] "+m" (val->count) 49 49 ); 50 50 … … 55 55 { 56 56 do { 57 while (val->count); 57 while (val->count) 58 ; 58 59 } while (test_and_set(val)); 59 60 } … … 64 65 65 66 asm volatile ( 66 "fetchadd8.rel %[v] = %[count], 1\n"67 : [v] "=r" (v),68 [count] "+m" (val->count)67 "fetchadd8.rel %[v] = %[count], 1\n" 68 : [v] "=r" (v), 69 [count] "+m" (val->count) 69 70 ); 70 71 } … … 75 76 76 77 asm volatile ( 77 "fetchadd8.rel %[v] = %[count], -1\n"78 : [v] "=r" (v),79 [count] "+m" (val->count)78 "fetchadd8.rel %[v] = %[count], -1\n" 79 : [v] "=r" (v), 80 [count] "+m" (val->count) 80 81 ); 81 82 } … … 86 87 87 88 asm volatile ( 88 "fetchadd8.rel %[v] = %[count], 1\n"89 : [v] "=r" (v),90 [count] "+m" (val->count)89 "fetchadd8.rel %[v] = %[count], 1\n" 90 : [v] "=r" (v), 91 [count] "+m" (val->count) 91 92 ); 92 93 … … 99 100 100 101 asm volatile ( 101 "fetchadd8.rel %[v] = %[count], -1\n"102 : [v] "=r" (v),103 [count] "+m" (val->count)102 "fetchadd8.rel %[v] = %[count], -1\n" 103 : [v] "=r" (v), 104 [count] "+m" (val->count) 104 105 ); 105 106 … … 112 113 113 114 asm volatile ( 114 "fetchadd8.rel %[v] = %[count], 1\n"115 : [v] "=r" (v),116 [count] "+m" (val->count)115 "fetchadd8.rel %[v] = %[count], 1\n" 116 : [v] "=r" (v), 117 [count] "+m" (val->count) 117 118 ); 118 119 … … 125 126 126 127 asm volatile ( 127 "fetchadd8.rel %[v] = %[count], -1\n"128 : [v] "=r" (v),129 [count] "+m" (val->count)128 "fetchadd8.rel %[v] = %[count], -1\n" 129 : [v] "=r" (v), 130 [count] "+m" (val->count) 130 131 ); 131 132 -
kernel/arch/ia64/include/arch/cpu.h
r47b2d7e3 r1433ecda 68 68 69 69 asm volatile ( 70 "mov %[v] = cpuid[%[r]]\n"71 : [v] "=r" (v)72 : [r] "r" (n)70 "mov %[v] = cpuid[%[r]]\n" 71 : [v] "=r" (v) 72 : [r] "r" (n) 73 73 ); 74 74 -
kernel/arch/ia64/include/arch/mm/page.h
r47b2d7e3 r1433ecda 56 56 57 57 #ifdef __ASSEMBLER__ 58 #define VRN_KERNEL 758 #define VRN_KERNEL 7 59 59 #else 60 #define VRN_KERNEL 7ULL60 #define VRN_KERNEL 7ULL 61 61 #endif 62 62 … … 97 97 unsigned long long tag : 63; 98 98 unsigned int ti : 1; 99 } __attribute__ ((packed));99 } __attribute__((packed)); 100 100 101 101 union vhpt_tag { … … 129 129 /* Word 3 */ 130 130 uint64_t ig3 : 64; 131 } __attribute__ ((packed));131 } __attribute__((packed)); 132 132 133 133 struct vhpt_entry_not_present { … … 147 147 /* Word 3 */ 148 148 uint64_t ig3 : 64; 149 } __attribute__ ((packed));149 } __attribute__((packed)); 150 150 151 151 typedef union { … … 161 161 unsigned int rid : 24; 162 162 unsigned int : 32; 163 } __attribute__ ((packed));163 } __attribute__((packed)); 164 164 165 165 typedef union { … … 175 175 unsigned int : 6; 176 176 unsigned long long base : 49; 177 } __attribute__ ((packed));177 } __attribute__((packed)); 178 178 179 179 typedef union pta_register { … … 196 196 197 197 asm volatile ( 198 "thash %[ret] = %[va]\n"199 : [ret] "=r" (ret)200 : [va] "r" (va)198 "thash %[ret] = %[va]\n" 199 : [ret] "=r" (ret) 200 : [va] "r" (va) 201 201 ); 202 202 … … 218 218 219 219 asm volatile ( 220 "ttag %[ret] = %[va]\n"221 : [ret] "=r" (ret)222 : [va] "r" (va)220 "ttag %[ret] = %[va]\n" 221 : [ret] "=r" (ret) 222 : [va] "r" (va) 223 223 ); 224 224 … … 239 239 240 240 asm volatile ( 241 "mov %[ret] = rr[%[index]]\n"242 : [ret] "=r" (ret)243 : [index] "r" (i << VRN_SHIFT)241 "mov %[ret] = rr[%[index]]\n" 242 : [ret] "=r" (ret) 243 : [index] "r" (i << VRN_SHIFT) 244 244 ); 245 245 … … 257 257 258 258 asm volatile ( 259 "mov rr[%[index]] = %[value]\n"260 :: [index] "r" (i << VRN_SHIFT),261 [value] "r" (v)259 "mov rr[%[index]] = %[value]\n" 260 :: [index] "r" (i << VRN_SHIFT), 261 [value] "r" (v) 262 262 ); 263 263 } … … 272 272 273 273 asm volatile ( 274 "mov %[ret] = cr.pta\n"275 : [ret] "=r" (ret)274 "mov %[ret] = cr.pta\n" 275 : [ret] "=r" (ret) 276 276 ); 277 277 … … 286 286 { 287 287 asm volatile ( 288 "mov cr.pta = %[value]\n"289 :: [value] "r" (v)288 "mov cr.pta = %[value]\n" 289 :: [value] "r" (v) 290 290 ); 291 291 } -
kernel/arch/ia64/include/arch/mm/tlb.h
r47b2d7e3 r1433ecda 69 69 unsigned int key : 24; /**< Protection key, unused. */ 70 70 unsigned int : 32; 71 } __attribute__ ((packed));72 } __attribute__ ((packed)) tlb_entry_t;71 } __attribute__((packed)); 72 } __attribute__((packed)) tlb_entry_t; 73 73 74 74 extern void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc); -
kernel/arch/ia64/include/arch/register.h
r47b2d7e3 r1433ecda 184 184 unsigned int bn : 1; /**< Register Bank. */ 185 185 unsigned int ia : 1; /**< Disable Instruction Access-bit faults. */ 186 } __attribute__ ((packed));186 } __attribute__((packed)); 187 187 } psr_t; 188 188 … … 196 196 unsigned int : 11; 197 197 unsigned int loadrs : 14; 198 } __attribute__ ((packed));198 } __attribute__((packed)); 199 199 } rsc_t; 200 200 … … 210 210 struct { 211 211 unsigned int : 4; 212 unsigned int mic : 4; /**< Mask Interrupt Class. */212 unsigned int mic : 4; /**< Mask Interrupt Class. */ 213 213 unsigned int : 8; 214 unsigned int mmi : 1; /**< Mask Maskable Interrupts. */215 } __attribute__ ((packed));214 unsigned int mmi : 1; /**< Mask Maskable Interrupts. */ 215 } __attribute__((packed)); 216 216 } cr_tpr_t; 217 217 … … 225 225 unsigned int : 3; 226 226 unsigned int m : 1; /**< Mask. */ 227 } __attribute__ ((packed));227 } __attribute__((packed)); 228 228 } cr_itv_t; 229 229 … … 238 238 unsigned int ge_na : 4; 239 239 unsigned int ge_code : 4; 240 } __attribute__ ((packed));240 } __attribute__((packed)); 241 241 }; 242 242 uint8_t vector; … … 254 254 unsigned int ed : 1; /**< Exception Deferral. */ 255 255 unsigned int : 20; 256 } __attribute__ ((packed));256 } __attribute__((packed)); 257 257 } cr_isr_t; 258 258 … … 266 266 uint8_t family; 267 267 uint8_t archrev; 268 } __attribute__ ((packed));268 } __attribute__((packed)); 269 269 } cpuid3_t; 270 270
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