Index: kernel/arch/arm32/src/arm32.c
===================================================================
--- kernel/arch/arm32/src/arm32.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/arm32.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -156,5 +156,6 @@
 {
 	/* not implemented */
-	while (true);
+	while (true)
+		;
 }
 
Index: kernel/arch/arm32/src/atomic.c
===================================================================
--- kernel/arch/arm32/src/atomic.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/atomic.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -44,5 +44,5 @@
  * returns the previous value of \a *ptr.
  */
-void * __sync_val_compare_and_swap_4(void **ptr, void *expected, void *new_val)
+void *__sync_val_compare_and_swap_4(void **ptr, void *expected, void *new_val)
 {
 	/*
@@ -55,5 +55,5 @@
 	irq_spinlock_lock(&cas_lock, true);
 
-	void * cur_val = *ptr;
+	void *cur_val = *ptr;
 
 	if (cur_val == expected) {
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -62,13 +62,19 @@
 
 /** Implementers (vendor) names */
-static const char * implementer(unsigned id)
+static const char *implementer(unsigned id)
 {
 	switch (id) {
-	case 0x41: return "ARM Limited";
-	case 0x44: return "Digital Equipment Corporation";
-	case 0x4d: return "Motorola, Freescale Semiconductor Inc.";
-	case 0x51: return "Qualcomm Inc.";
-	case 0x56: return "Marvell Semiconductor Inc.";
-	case 0x69: return "Intel Corporation";
+	case 0x41:
+		return "ARM Limited";
+	case 0x44:
+		return "Digital Equipment Corporation";
+	case 0x4d:
+		return "Motorola, Freescale Semiconductor Inc.";
+	case 0x51:
+		return "Qualcomm Inc.";
+	case 0x56:
+		return "Marvell Semiconductor Inc.";
+	case 0x69:
+		return "Intel Corporation";
 	}
 	return "Unknown implementer";
@@ -76,5 +82,5 @@
 
 /** Architecture names */
-static const char * architecture_string(cpu_arch_t *arch)
+static const char *architecture_string(cpu_arch_t *arch)
 {
 	static const char *arch_data[] = {
Index: kernel/arch/arm32/src/fpu_context.c
===================================================================
--- kernel/arch/arm32/src/fpu_context.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/fpu_context.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -126,5 +126,5 @@
 	 * Moreover they need to have same access enabled */
 	if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
-	   ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
+	    ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
 		printf("No access to CP10 and CP11: %" PRIx32 "\n", cpacr);
 		return 0;
Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c
===================================================================
--- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -130,5 +130,6 @@
 static void bbxm_cpu_halt(void)
 {
-	while (1);
+	while (1)
+		;
 }
 
Index: kernel/arch/arm32/src/mach/beaglebone/beaglebone.c
===================================================================
--- kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -137,5 +137,5 @@
 	/* Select the SYSCLK as the clock source for the dmtimer2 module */
 	am335x_clock_source_select(bbone.cm_dpll_addr, DMTIMER2,
-	   CLK_SRC_M_OSC);
+	    CLK_SRC_M_OSC);
 	/* Initialize the DMTIMER2 */
 	if (am335x_ctrl_module_clock_freq_get(bbone.ctrl_module,
@@ -159,5 +159,6 @@
 static void bbone_cpu_halt(void)
 {
-	while (1);
+	while (1)
+		;
 }
 
Index: kernel/arch/arm32/src/machine_func.c
===================================================================
--- kernel/arch/arm32/src/machine_func.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/machine_func.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -137,5 +137,5 @@
 }
 
-const char * machine_get_platform_name(void)
+const char *machine_get_platform_name(void)
 {
 	if (machine_ops->machine_get_platform_name)
Index: kernel/arch/arm32/src/mm/page_fault.c
===================================================================
--- kernel/arch/arm32/src/mm/page_fault.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/mm/page_fault.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -75,5 +75,5 @@
 } dfsr_source_t;
 
-static inline const char * dfsr_source_to_str(dfsr_source_t source)
+static inline const char *dfsr_source_to_str(dfsr_source_t source)
 {
 	switch (source)	{
@@ -149,5 +149,5 @@
 		panic("page_fault - instruction does not access memory "
 		    "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
-		    *(uint32_t*)instr_union.instr, (void *) badvaddr);
+		    *(uint32_t *)instr_union.instr, (void *) badvaddr);
 		return PF_ACCESS_EXEC;
 	}
@@ -177,5 +177,5 @@
 		{ 0x0fb00000, 0x01000000, PF_ACCESS_WRITE },
 	};
-	const uint32_t inst = *(uint32_t*)instr_addr;
+	const uint32_t inst = *(uint32_t *)instr_addr;
 	for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) {
 		if ((inst & ls_inst[i].mask) == ls_inst[i].value) {
Index: kernel/arch/arm32/src/userspace.c
===================================================================
--- kernel/arch/arm32/src/userspace.c	(revision 9ce35f067406cfc2d4e59addfe1e84524ba08fa4)
+++ kernel/arch/arm32/src/userspace.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
@@ -104,15 +104,15 @@
 	/* set user mode, set registers, jump */
 	asm volatile (
-		"mov sp, %[ustate]\n"
-		"msr spsr_c, %[user_mode]\n"
-		"ldmfd sp, {r0-r12, sp, lr}^\n"
-		"nop\n"		/* Cannot access sp immediately after ldm(2) */
-		"add sp, sp, #(15*4)\n"
-		"ldmfd sp!, {pc}^\n"
-		:: [ustate] "r" (&ustate), [user_mode] "r" (user_mode)
+	    "mov sp, %[ustate]\n"
+	    "msr spsr_c, %[user_mode]\n"
+	    "ldmfd sp, {r0-r12, sp, lr}^\n"
+	    "nop\n"		/* Cannot access sp immediately after ldm(2) */
+	    "add sp, sp, #(15*4)\n"
+	    "ldmfd sp!, {pc}^\n"
+	    :: [ustate] "r" (&ustate), [user_mode] "r" (user_mode)
 	);
 
 	/* unreachable */
-	while(1)
+	while (1)
 		;
 }