Changeset 124bc22 in mainline for kernel/arch/mips32/src/mach

Timestamp:

2019-04-04T18:08:51Z (7 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5d97627

Parents:

e064102

Message:

Reorganize interrupt and IRQ handling on mips32

This allows msim to use MIPS CPU interrupt numbers as IRQ numbers and
Malta to use ISA IRQ numbers as IRQ numbers. Common code can still
register MIPS CPU interrupts by their respective numbers.

Location:

kernel/arch/mips32/src/mach

Files:

• malta/malta.c (modified) (4 diffs)
• msim/msim.c (modified) (2 diffs)

kernel/arch/mips32/src/mach/malta/malta.c

@@ -42 +42 @@
 #include <genarch/srln/srln.h>
 #include <arch/interrupt.h>
+#include <stdbool.h>
+#include <byteorder.h>
+#include <log.h>
 
 static void malta_init(void);
@@ -68 +71 @@
 #endif
 
-#ifdef CONFIG_NS16550
-static void tty_clear_interrupt(void *arg, inr_t inr)
+static void malta_isa_irq_handler(unsigned int i)
 {
-        (void) pio_read_8((ioport8_t *) GT64120_PCI0_INTACK);
+        uint8_t isa_irq = host2uint32_t_le(pio_read_32(GT64120_PCI0_INTACK));
+        irq_t *irq = irq_dispatch_and_lock(isa_irq);
+        if (irq) {
+                irq->handler(irq);
+                irq_spinlock_unlock(&irq->lock, false);
+        } else {
+#ifdef CONFIG_DEBUG
+                log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious IRQ (irq=%u)",
+                    CPU->id, isa_irq);
+#endif
+        }
         pic_eoi();
 }
-#endif
 
 void malta_init(void)
 {
+        irq_init(16, 16);
+
         i8259_init((i8259_t *) PIC0_BASE, (i8259_t *) PIC1_BASE, 2, 0, 8);
+
+        int_handler[INT_HW0] = malta_isa_irq_handler;
+        cp0_unmask_int(INT_HW0);
 
 #if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
@@ -86 +102 @@
         outdev_t **tty_out_ptr = NULL;
 #endif
-        tty_instance = ns16550_init((ioport8_t *) TTY_BASE, 0, TTY_CPU_INT,
-            tty_clear_interrupt, NULL, tty_out_ptr);
+        tty_instance = ns16550_init((ioport8_t *) TTY_BASE, 0, TTY_ISA_IRQ,
+            NULL, NULL, tty_out_ptr);
 #endif
 }
@@ -121 +137 @@
                         ns16550_wire(tty_instance, srln);
                         pic_enable_irqs(1 << TTY_ISA_IRQ);
-                        cp0_unmask_int(TTY_CPU_INT);
                 }
         }

kernel/arch/mips32/src/mach/msim/msim.c

@@ -41 +41 @@
 #include <genarch/drivers/dsrln/dsrlnout.h>
 #include <genarch/srln/srln.h>
+#include <stdbool.h>
 
 static void msim_init(void);
@@ -60 +61 @@
 };
 
+static void msim_irq_handler(unsigned int i)
+{
+        irq_t *irq = irq_dispatch_and_lock(i);
+        if (irq) {
+                irq->handler(irq);
+                irq_spinlock_unlock(&irq->lock, false);
+        } else {
+#ifdef CONFIG_DEBUG
+                log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious IRQ (irq=%u)",
+                    CPU->id, i);
+#endif
+        }
+}
+
 void msim_init(void)
 {
+        irq_init(HW_INTERRUPTS, HW_INTERRUPTS);
+
+        int_handler[INT_HW0] = msim_irq_handler;
+        int_handler[INT_HW1] = msim_irq_handler;
+        int_handler[INT_HW2] = msim_irq_handler;
+        int_handler[INT_HW3] = msim_irq_handler;
+        int_handler[INT_HW4] = msim_irq_handler;
+
         dorder_init();
         cp0_unmask_int(MSIM_DDISK_IRQ);